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hys64t32[0/9]00eu-[25f/2.5/3/3s/3.7]-b2 hys[64/72]t64[0/9]00eu -[25f/2.5/3/3s/3.7]-b2 hys[64/72]t128[0/9]20eu-[25f/2.5/3/3s/3.7]-b2 240-pin unbuffered ddr2 sdram modules udimm sdram rohs compliant internet data sheet rev. 1.01 january 2008
internet data sheet hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module qag_techdoc_rev411 / 3.31 qag / 2007-01-22 2 10202006-l0sm-feyt we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com hys64t32[0/9]00eu-[25f/2.5/3/3s/3.7]-b2 , hys[64/72]t64[0/9]00eu-[25f/2.5/3/3s/3.7]-b2 , hys[64/72]t128[0/9]20eu- [25f/2.5/3/3s/3.7]-b2 revision history: 2008-01, rev. 1.01 page subjects (major chang es since last revision) all editorial change and adapted to internet edition previous revision: 2006-10, rev. 1.0 all qimonda update 4,5 ordering information table. added 6layerwhitebox products. 16 ? 20 block diagrams: clock signal load tables and notes updated 34,35 odt table update 38 ? 42 added idd values. 45 ? 92 spd codes updated. previous revision: 2006-07, rev. 0.5
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 3 10202006-l0sm-feyt 1 overview this chapter gives an overview of the 240-pin unbuffered ddr2 sdram modules product family and describes its main characteristics. 1.1 features ? 240-pin pc2-6400, pc2-5300 and pc2-4200 ddr2 sdram memory modules. ? two ranks 128m 64, 128m 72, and one rank 32m 64, 64m 64, 64m 72 module organization, and 32m 16, 64m 8 chip organization ? 1gb, 512mb, 256mb modules built with 512mbit ddr2 sdrams in p-tfbga-60 a nd pg-tfbga-84 chipsize packages. ? standard double-data-rate-two synchronous drams (ddr2 sdram) with a single + 1.8 v ( 0.1 v) power supply. ? all speed grades faster than ddr2-400 comply with ddr2-400 timing specifications. ? programmable cas latencies (3, 4, 5 and 6 ), burst length (8 & 4). ? auto refresh (cbr) and self refresh. ? auto refresh for temperatures above 85 c t refi = 3.9 s. ? programmable self refres h rate via emrs2 setting. ? programmable partial array refresh via emrs2 settings. ? dcc enabling via emrs2 setting. ? all inputs and outputs sstl_1.8 compatible. ? off-chip driver impedance adjustment (ocd) and on-die termination (odt). ? serial presence detect with e 2 prom ? udimm and edimm dimensions (nominal): 30 mm high, 133.35 mm wide. ? based on standard reference layouts raw cards 'c', 'd', 'e', ?f' and 'g' ? rohs compliant products 1) table 1 performance table 1) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers. qag speed code ?25f ?2.5 ?3 ?3s ?3.7 unit dram speed grade ddr2 ?800d ?800e ?667c ?667d ?533c module speed grade pc2 ?6400d ?6400e ?5300c ?5300d ?4200c cas-rcd-rp latencies 5?5?5 6?6?6 4?4?4 5?5?5 4?4?4 t ck max. clock frequency cl3 f ck3 200 200 200 200 200 mhz cl4 f ck4 266 266 333 266 266 mhz cl5 f ck5 400 333 333 333 266 mhz cl6 f ck6 ?400???mhz min. ras-cas-delay t rcd 12.515121515ns min. row precharge time t rp 12.515121515ns min. row active time 1) 1) product released after 01-08-2007 will support t ras = 40 ns for all ddr2 speed sort. t ras 45 45 45 45 45 ns min. row cycle time t rc 57.560576060ns
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 4 10202006-l0sm-feyt 1.2 description the qimonda hys[64 /72]t[32/64 /128]xxxeu- [25f/2.5/3/3s/3.7]-b2 module family are unbuffered dimm modules ?udimms? with 30 mm height based on ddr2 technology. dimms are available as non-ecc modules in 128m 72 (1gb), 32m 64 (256mb), 64m 64 (512mb) and as ecc modules in 128m 72 (1gb), 64m 72 (512mb) in organization and density, intended for mounting into 240-pin connector sockets. the memory array is designed with 512mbit double-data- rate-two (ddr2) synchronous drams. decoupling capacitors are mounted on the pcb board. the dimms feature serial presence detect based on a serial e 2 prom device using the 2-pin i 2 c protocol. the first 128 bytes are programmed with configuration da ta and are write protected; the second 128 bytes are available to the customer. table 2 ordering information product type 1) compliance code 2) description sdram technology pc2-6400 (5-5-5) hys72t128920eu?25f?b2 1gb 2r 8 pc2?6400e?555?12?g0 2 ranks, non-ecc 512mbit ( 8) hys64t128920eu?25f?b2 1gb 2r 8 pc2?6400u?555?12?e0 2 ranks, non-ecc 512mbit ( 8) hys72t128020eu?25f?b2 1gb 2r 8 pc2?6400e?555?12?g0 2 ranks, non-ecc 512mbit ( 8) hys64t128020eu?25f?b2 1gb 2r 8 pc2?6400u?555?12?e0 2 ranks, non-ecc 512mbit ( 8) hys72t64900eu?25f?b2 512mb 1r 8 pc2?6400e?555?12?f0 1 rank, non-ecc 512mbit ( 8) hys64t64900eu?25f?b2 512mb 1r 8 pc2?6400u?555?12?d0 1 rank, non-ecc 512mbit ( 8) hys72t64000eu?25f?b2 512mb 1r 8 pc2?6400e?555?12?f0 1 rank, non-ecc 512mbit ( 8) hys64t64000eu?25f?b2 512mb 1r 8 pc2?6400u?555?12?d0 1 rank, non-ecc 512mbit ( 8) hys64t32900eu?25f?b2 256mb 1r 16 pc2?6400u?555?12?c1 1 rank, non-ecc 512mbit ( 16) hys64t32000eu?25f?b2 256mb 1r 16 pc2?6400u?555?12?c1 1 rank, non-ecc 512mbit ( 16) pc2-6400 (6-6-6) hys72t128920eu?2.5?b2 1gb 2r 8 pc2?6400e?666?12?g0 2 ranks, non-ecc 512mbit ( 8) hys64t128920eu?2.5?b2 1gb 2r 8 pc2?6400u?666?12?e0 2 ranks, non-ecc 512mbit ( 8) hys72t128020eu?2.5?b2 1gb 2r 8 pc2?6400e?666?12?g0 2 ranks, non-ecc 512mbit ( 8) hys64t128020eu?2.5?b2 1gb 2r 8 pc2?6400u?666?12?e0 2 ranks, non-ecc 512mbit ( 8) hys72t64900eu?2.5?b2 512mb 1r 8 pc2?6400e?666?12?f0 1 rank, non-ecc 512mbit ( 8) hys64t64900eu?2.5?b2 512mb 1r 8 pc2?6400u?666?12?d0 1 rank, non-ecc 512mbit ( 8) hys72t64000eu?2.5?b2 512mb 1r 8 pc2?6400e?666?12?f0 1 rank, non-ecc 512mbit ( 8) hys64t64000eu?2.5?b2 512mb 1r 8 pc2?6400u?666?12?d0 1 rank, non-ecc 512mbit ( 8) hys64t32900eu?2.5?b2 256mb 1r 16 pc2?6400u?666?12?c1 1 rank, non-ecc 512mbit ( 16) hys64t32000eu?2.5?b2 256mb 1r 16 pc2?6400u?666?12?c1 1 rank, non-ecc 512mbit ( 16) pc2-5300 (4-4-4) hys72t128920eu?3?b2 1gb 2r 8 pc2?5300e?444?12?g0 2 ranks, non-ecc 512mbit ( 8) hys64t128920eu?3?b2 1gb 2r 8 pc2?5300u?444?12?e0 2 ranks, non-ecc 512mbit ( 8) hys72t128020eu?3?b2 1gb 2r 8 pc2?5300e?444?12?g0 2 ranks, non-ecc 512mbit ( 8)
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 5 10202006-l0sm-feyt table 3 address format hys64t128020eu?3?b2 1gb 2r 8 pc2?5300u?444?12?e0 2 ranks, non-ecc 512mbit ( 8) hys72t64900eu?3?b2 512mb 1r 8 pc2?5300e?444?12?f0 1 rank, non-ecc 512mbit ( 8) hys64t64900eu?3?b2 512mb 1r 8 pc2?5300u?444?12?d0 1 rank, non-ecc 512mbit ( 8) hys72t64000eu?3?b2 512mb 1r 8 pc2?5300e?444?12?f0 1 rank, non-ecc 512mbit ( 8) hys64t64000eu?3?b2 512mb 1r 8 pc2?5300u?444?12?d0 1 rank, non-ecc 512mbit ( 8) hys64t32900eu?3?b2 256mb 1r 16 pc2?5300u?444?12?c1 1 rank, non-ecc 512mbit ( 16) hys64t32000eu?3?b2 256mb 1r 16 pc2?5300u?444?12?c1 1 rank, non-ecc 512mbit ( 16) pc2-5300 (5-5-5) hys72t128920eu?3s?b2 1gb 2r 8 pc2?5300e?555?12?g0 2 ranks, non-ecc 512mbit ( 8) hys64t128920eu?3s?b2 1gb 2r 8 pc2?5300u?555?12?e0 2 ranks, non-ecc 512mbit ( 8) hys72t128020eu?3s?b2 1gb 2r 8 pc2?5300e?555?12?g0 2 ranks, non-ecc 512mbit ( 8) hys64t128020eu?3s?b2 1gb 2r 8 pc2?5300u?555?12?e0 2 ranks, non-ecc 512mbit ( 8) hys72t64900eu?3s?b2 512mb 1r 8 pc2?5300e?555?12?f0 1 rank, non-ecc 512mbit ( 8) hys64t64900eu?3s?b2 512mb 1r 8 pc2?5300u?555?12?d0 1 rank, non-ecc 512mbit ( 8) hys72t64000eu?3s?b2 512mb 1r 8 pc2?5300e?555?12?f0 1 rank, non-ecc 512mbit ( 8) hys64t64000eu?3s?b2 512mb 1r 8 pc2?5300u?555?12?d0 1 rank, non-ecc 512mbit ( 8) hys64t32900eu?3s?b2 256mb 1r 16 pc2?5300u?555?12?c1 1 rank, non-ecc 512mbit ( 16) hys64t32000eu?3s?b2 256mb 1r 16 pc2?5300u?555?12?c1 1 rank, non-ecc 512mbit ( 16) pc2-4200 (4-4-4) hys72t128920eu?3.7?b2 1gb 2r 8 pc2?4200e?444?12?g0 2 ranks, non-ecc 512mbit ( 8) hys64t128920eu?3.7?b2 1gb 2r 8 pc2?4200u?444?12?e0 2 ranks, non-ecc 512mbit ( 8) hys72t128020eu?3.7?b2 1gb 2r 8 pc2?4200e?444?12?g0 2 ranks, non-ecc 512mbit ( 8) hys64t128020eu?3.7?b2 1gb 2r 8 pc2?4200u?444?12?e0 2 ranks, non-ecc 512mbit ( 8) hys72t64900eu?3.7?b2 512mb 1r 8 pc2?4200e?444?12?f0 1 rank, non-ecc 512mbit ( 8) hys64t64900eu?3.7?b2 512mb 1r 8 pc2?4200u?444?12?d0 1 rank, non-ecc 512mbit ( 8) hys72t64000eu?3.7?b2 512mb 1r 8 pc2?4200e?444?12?f0 1 rank, non-ecc 512mbit ( 8) hys64t64000eu?3.7?b2 512mb 1r 8 pc2?4200u?444?12?d0 1 rank, non-ecc 512mbit ( 8) hys64t32900eu?3.7?b2 256mb 1r 16 pc2?4200u?444?12?c1 1 rank, non-ecc 512mbit ( 16) hys64t32000eu?3.7?b2 256mb 1r 16 pc2?4200u?444?12?c1 1 rank, non-ecc 512mbit ( 16) 1) for detailed information regarding product type of qimonda pleas e see chapter "product type nomenclature" of this datasheet. 2) the compliance code is printed on the module label and des cribes the speed grade, for example "pc2?6400e?555?12?g0" where 640 0e means unbuffered dimm modules with 6.40 gb/s ec module bandwidth and "555?12" means column address strobe (cas) latency =5, row column delay (rcd) latency = 5 and row precharge (rp) laten cy = 5 using the latest jedec spd revision 1.2 and produced on the raw card "g". dimm density module organization memory ranks ecc/ non-ecc # of sdrams # of row/bank/column bits raw card 1gb 128m 72 2 ecc 18 14/2/10 g 1gb 128m 64 2 non-ecc 16 14/2/10 e product type 1) compliance code 2) description sdram technology
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 6 10202006-l0sm-feyt table 4 components on modules 512mb 64m 72 1 ecc 9 14/2/10 f 512mb 64m 64 1 non-ecc 8 14/2/10 d 256mb 32m 64 1 non-ecc 4 13/2/10 c product type 1)2) 1) green product 2) for a detailed description of all functionalities of the dram components on these modules see the component data sheet. dram components 1) dram density dram organisation hys72t128920eu hyb18t512800b2f 512mbit 64m 8 hys64t128920eu hyb18t512800b2f 512mbit 64m 8 hys72t128020eu hyb18t512800b2f 512mbit 64m 8 hys64t128020eu hyb18t512800b2f 512mbit 64m 8 hys72t64900eu hyb18t512800b2f 512mbit 64m 8 hys64t64900eu hyb18t512800b2f 512mbit 64m 8 hys72t64000eu hyb18t512800b2f 512mbit 64m 8 hys64t64000eu hyb18t512800b2f 512mbit 64m 8 hys64t32900eu hyb18t512160b2f 512mbit 32m 16 hys64t32000eu hyb18t512160b2f 512mbit 32m 16 dimm density module organization memory ranks ecc/ non-ecc # of sdrams # of row/bank/column bits raw card
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 7 10202006-l0sm-feyt 2 pin configurations 2.1 pin configurations the pin configuration of the unbuffered ddr2 sdram dimm is listed by function in table 5 (240 pins). the abbreviations used in columns pin and buffer type are explained in table 6 and table 7 respectively. the pin numbering is depicted in figure 1 for non-ecc modules ( 64) and figure 2 for ecc modules ( 72). table 5 pin configuration of udimm ball no. name pin type buffer type function clock signals 185 ck0 i sstl clock signals 2:0, complement clock signals 2:0 the system clock inputs. a ll address and command li nes are sampled on the cross point of the rising edge of ck and the falling edge of ck . a delay locked loop (dll) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. 137 ck1 i sstl 220 ck2 i sstl 186 ck0 i sstl 138 ck1 i sstl 221 ck2 i sstl 52 cke0 i sstl clock enable rank 1:0 activates the ddr2 sdram ck signal when high and deactivates the ck signal when low. by deactivating the clocks, cke low initiates the power down mode or the self refresh mode. note: 2 ranks module 171 cke1 i sstl nc nc ? not connected note: 1 rank module control signals 193 s0 i sstl chip select rank 1:0 enables the associated ddr2 sdram command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. rank 0 is selected by s0 ; rank 1 is selected by s1 . ranks are also called "physical banks". note: 2 ranks module 76 s1 i sstl nc nc ? not connected note: 1 rank module 192 ras i sstl row address strobe when sampled at the cross point of th e rising edge of ck,and falling edge of ck , ras , cas and we define the operation to be executed by the sdram. 74 cas i sstl column address strobe
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 8 10202006-l0sm-feyt 73 we i sstl write enable address signals 71 ba0 i sstl bank address bus 1:0 selects which ddr2 sdram internal bank of four or eight is activated. 190 ba1 i sstl 54 ba2 i sstl bank address bus 2 greater than 512mb ddr2 sdrams nc nc ? not connected less than 1gb ddr2 sdrams 188 a0 i sstl address bus 12:0 during a bank activate command cycle, defines the row address when sampled at the crosspoint of the risi ng edge of ck and falling edge of ck . during a read or write command cycle, defines the column address when sampled at the cross point of the ri sing edge of ck and falling edge of ck . in addition to the column address, ap is used to invoke autoprecharge operation at the end of the burst read or write cycle. if ap is high , autoprecharge is selected and ba0-ban defines the bank to be precharged. if ap is low, autoprecharge is disabled. during a precharge command cycle, ap is used in conjunction with ba0-ban to control which bank(s) to precharge. if ap is high, all banks will be precharged regardl ess of the state of ba0-ban inputs. if ap is low, then ba0-ban are used to define which bank to precharge. 183 a1 i sstl 63 a2 i sstl 182 a3 i sstl 61 a4 i sstl 60 a5 i sstl 180 a6 i sstl 58 a7 i sstl 179 a8 i sstl 177 a9 i sstl 70 a10 i sstl ap i sstl 57 a11 i sstl 176 a12 i sstl 196 a13 i sstl address signal 13 note: 1 gbit based module and 512m uu nc nc ? not connected note: module based on 1 gbit u 16module based on 512 mbit u 16 or smaller 174 a14 i sstl address signal 14 note: modules based on 2 gbit nc nc ? not connected note: modules based on 1 gbit or smaller data signals 3 dq0 i/o sstl data bus 63:0 data input / output pins 4 dq1 i/o sstl 9 dq2 i/o sstl 10 dq3 i/o sstl 122 dq4 i/o sstl 123 dq5 i/o sstl 128 dq6 i/o sstl 129 dq7 i/o sstl ball no. name pin type buffer type function
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 9 10202006-l0sm-feyt 12 dq8 i/o sstl data bus 63:0 data input / output pins 13 dq9 i/o sstl 21 dq10 i/o sstl 22 dq11 i/o sstl 131 dq12 i/o sstl 132 dq13 i/o sstl 140 dq14 i/o sstl 141 dq15 i/o sstl 24 dq16 i/o sstl 25 dq17 i/o sstl 30 dq18 i/o sstl 31 dq19 i/o sstl 143 dq20 i/o sstl 144 dq21 i/o sstl 149 dq22 i/o sstl 150 dq23 i/o sstl 33 dq24 i/o sstl 34 dq25 i/o sstl 39 dq26 i/o sstl 40 dq27 i/o sstl 152 dq28 i/o sstl 153 dq29 i/o sstl 158 dq30 i/o sstl 159 dq31 i/o sstl 80 dq32 i/o sstl 81 dq33 i/o sstl 86 dq34 i/o sstl 87 dq35 i/o sstl 199 dq36 i/o sstl 200 dq37 i/o sstl 205 dq38 i/o sstl 206 dq39 i/o sstl 89 dq40 i/o sstl 90 dq41 i/o sstl 95 dq42 i/o sstl 96 dq43 i/o sstl 208 dq44 i/o sstl 209 dq45 i/o sstl 214 dq46 i/o sstl 215 dq47 i/o sstl ball no. name pin type buffer type function
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 10 10202006-l0sm-feyt 98 dq48 i/o sstl data bus 63:0 data input / output pins 99 dq49 i/o sstl 107 dq50 i/o sstl 108 dq51 i/o sstl 217 dq52 i/o sstl 218 dq53 i/o sstl 226 dq54 i/o sstl 227 dq55 i/o sstl 110 dq56 i/o sstl 111 dq57 i/o sstl 116 dq58 i/o sstl 117 dq59 i/o sstl 229 dq60 i/o sstl 230 dq61 i/o sstl 235 dq62 i/o sstl 236 dq63 i/o sstl check bit signals 42 cb0 i/o sstl check bit 0 note: ecc type module only nc nc ? not connected note: ecc type module only 43 cb1 i/o sstl check bit 1 note: ecc type module only nc nc ? not connected note: ecc type module only 48 cb2 i/o sstl check bit 2 note: ecc type module only nc nc ? not connected note: ecc type module only 49 cb3 i/o sstl check bit 3 note: ecc type module only nc nc ? not connected note: ecc type module only 161 cb4 i/o sstl check bit 4 note: ecc type module only nc nc ? not connected note: ecc type module only 162 cb5 i/o sstl check bit 5 note: ecc type module only nc nc ? not connected note: ecc type module only ball no. name pin type buffer type function
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 11 10202006-l0sm-feyt 167 cb6 i/o sstl check bit 6 note: ecc type module only nc nc ? not connected note: ecc type module only 168 cb7 i/o sstl check bit 7 note: ecc type module only nc nc ? not connected note: non-ecc module data strobe bus 7 dqs0 i/o sstl data strobe bus 8:0 the data strobes, associated with one data byte, sourced with data transfers. in write mode, the data strobe is source d by the controller and is centered in the data window. in read mode the data strobe is sourced by the ddr2 sdram and is sent at the leadi ng edge of the data window. dqs signals are complements, and timing is relative to the crosspoint of respective dqs and dqs . if the module is to be operated in single ended strobe mode, all dqs signals must be tied on the system board to v ss and ddr2 sdram mode registers programmed appropriately. note: see block diagram for corresponding dq signals 16 dqs1 i/o sstl 28 dqs2 i/o sstl 37 dqs3 i/o sstl 84 dqs4 i/o sstl 93 dqs5 i/o sstl 105 dqs6 i/o sstl 114 dqs7 i/o sstl 46 dqs8 i/o sstl 6 dqs0 i/o sstl complement data strobe bus 8:0 note: see block diagram for corresponding dq signals 15 dqs1 i/o sstl 27 dqs2 i/o sstl 36 dqs3 i/o sstl 83 dqs4 i/o sstl 92 dqs5 i/o sstl 104 dqs6 i/o sstl 113 dqs7 i/o sstl 45 dqs8 i/o sstl data mask signals 125 dm0 i sstl data mask bus 8:0 the data write masks, a ssociated with one data byte. in write mode, dm operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. in read mode, dm lines have no effect. note: see block diagram for corresponding dq m signals 134 dm1 i sstl 146 dm2 i sstl 155 dm3 i sstl 202 dm4 i sstl 211 dm5 i sstl 223 dm6 i sstl 232 dm7 i sstl 164 dm8 i sstl eeprom 120 scl i cmos serial bus clock this signal is used to clock data into and out of the spd eeprom. ball no. name pin type buffer type function
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 12 10202006-l0sm-feyt 119 sda i/o od serial bus data this is a bidirectional pin used to transfer data into or out of the spd eeprom. a resistor must be connected from sda to v ddspd on the motherboard to act as a pull-up. 239 sa0 i cmos serial address select bus 2:0 address pins used to select the serial presence detect base address. 240 sa1 i cmos 101 sa2 i cmos power supplies 1 v ref ai ? i/o reference voltage reference voltage for the sstl-18 inputs. 238 v ddspd pwr ? eeprom power supply power supplies for core, i/o, serial presence detect, and ground for the module. 51,56,62,72,75,, 78,170,175,181,, 191,194 v ddq pwr ? i/o driver power supply 53,59,64,67,69,, 172,178,184,187, 189,197 v dd pwr ? power supply power supplies for core, i/o, serial presence detect, and ground for the module. 2,5,8,11,14,17,, 20,23,26,29,32, 35,38,41,44,47,, 50,65,66,79,82, 85,88,91,94,97,, 100,103,106, 109,112,115,118, 121,124,127,, 130,133,136,139, 142,145,148,, 151,154,157,160, 163,166,169, 198,201,204,207, 210,213,216,, 219,222,225,228, 231,234,237 v ss gnd ? ground plane power supplies for core, i/o, serial presence detect, and ground for the module. other pins 195 odt0 i sstl on-die termination control 0 77 odt1 i sstl on-die termination control 1 asserts on-die termination for dq, dm, dqs, and dqs signals if enabled via the ddr2 sdram mode register. note: 2 rank modules nc nc ? not connected note: 1 rank modules 18,19,55,68,102,1 26,135,147, 156,165,173,203, 212, 224,233 nc nc ? not connected note: pins not connected on infineon udimms ball no. name pin type buffer type function
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 13 10202006-l0sm-feyt table 6 abbreviations for pin type table 7 abbreviations for buffer type abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. pwr power gnd ground nc not connected abbreviation description sstl serial stub terminated logic (sstl_18) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin has 2 oper ational states, active low and tri-state, and allows multiple devices to share as a wire-or.
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 14 10202006-l0sm-feyt figure 1 pin configuration udimm u 72 (240 pin) 0 3 3 7 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 9 5 ( ) ' 4 9 6 6 ' 4 6 ' 4 9 6 6 ' 4 ' 4 6 9 6 6 1 & 9 6 6 ' 4 ' 4 6 9 6 6 ' 4 ' 4 9 6 6 ' 4 6 1 & 9 6 6 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q ' 4 ' 4 9 6 6 ' 4 6 9 6 6 9 6 6 ' 4 ' 4 6 9 6 6 ' 4 & % 9 6 6 ' 4 6 & % 9 6 6 & . ( 1 & % $ 9 ' ' 4 $ $ 9 ' ' 4 9 ' ' 9 6 6 1 & $ $3 9 ' ' 4 & $6 1 & 6 9 ' ' 4 ' 4 9 6 6 ' 4 6 ' 4 9 6 6 ' 4 ' 4 6 9 6 6 ' 4 ' 4 9 6 6 1 & ' 4 6 9 6 6 ' 4 ' 4 9 6 6 ' 4 6 ' 4 9 6 6 6 & / 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q ' 4 9 6 6 ' 4 ' 4 6 9 6 6 ' 4 ' 4 9 6 6 ' 4 6 ' 4 9 6 6 & % ' 4 6 9 6 6 & % 9 ' ' 4 9 ' ' 1 & $ 9 ' ' $ $ 9 6 6 9 ' ' 9 ' ' % $ : ( 9 ' ' 4 2 ' 7 9 6 6 ' 4 ' 4 6 9 6 6 ' 4 ' 4 9 6 6 ' 4 6 9 6 6 9 6 6 ' 4 6 $ 9 6 6 ' 4 6 ' 4 9 6 6 ' 4 ' 4 6 9 6 6 ' 4 6 ' $ 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 9 6 6 ' 4 ' 0 9 6 6 ' 4 ' 4 9 6 6 1 & & . 9 6 6 ' 4 9 6 6 1 & ' 4 9 6 6 ' 4 ' 0 1 & & . ' 4 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 9 6 6 ' 4 ' 0 9 6 6 ' 4 ' 4 9 6 6 1 & ' 4 9 6 6 & % ' 0 9 6 6 & % 9 ' ' 4 9 ' ' $ $ 9 ' ' $ $ 9 ' ' & . $ % $ 5 $6 9 ' ' 4 1 & $ 9 6 6 ' 4 ' 0 9 6 6 ' 4 ' 4 9 6 6 1 & ' 4 9 6 6 ' 4 & . 9 6 6 1 & ' 4 9 6 6 ' 4 ' 0 9 6 6 ' 4 9 ' ' 6 3 ' 6 $ 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q ' 4 ' 4 9 6 6 1 & ' 4 9 6 6 ' 4 ' 0 9 6 6 ' 4 & % 9 6 6 1 & & % 9 6 6 & . ( 1 & 9 ' ' 4 $ $ 9 ' ' 4 $ & . 9 ' ' 9 ' ' 9 ' ' 4 6 2 ' 7 9 ' ' ' 4 9 6 6 1 & ' 4 9 6 6 ' 4 ' 0 9 6 6 ' 4 ' 4 9 6 6 & . ' 0 9 6 6 ' 4 ' 4 9 6 6 1 & ' 4 9 6 6 6 $ ) 5 2 1 7 6 , ' ( % $ & . 6 , ' (
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 15 10202006-l0sm-feyt figure 2 pin configuration udimm u 64 (240 pin) 0 3 3 7 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 9 5 ( ) ' 4 9 6 6 ' 4 6 ' 4 9 6 6 ' 4 ' 4 6 9 6 6 1 & 9 6 6 ' 4 ' 4 6 9 6 6 ' 4 ' 4 9 6 6 ' 4 6 1 & 9 6 6 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q ' 4 ' 4 9 6 6 ' 4 6 ' 4 9 6 6 ' 4 ' 4 6 9 6 6 ' 4 1 & 9 6 6 1 & 1 & 9 6 6 & . ( 1 & % $ 9 ' ' 4 $ $ 9 ' ' 4 9 ' ' 9 6 6 1 & $ $3 9 ' ' 4 & $6 1 & 6 9 ' ' 4 ' 4 9 6 6 ' 4 6 ' 4 9 6 6 ' 4 ' 4 6 9 6 6 ' 4 ' 4 9 6 6 1 & ' 4 6 9 6 6 ' 4 ' 4 9 6 6 ' 4 6 ' 4 9 6 6 6 & / 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q ' 4 9 6 6 ' 4 ' 4 6 9 6 6 ' 4 ' 4 9 6 6 ' 4 6 ' 4 9 6 6 1 & 1 & 9 6 6 1 & 9 ' ' 4 9 ' ' 1 & $ 9 ' ' $ $ 9 6 6 9 ' ' 9 ' ' % $ : ( 9 ' ' 4 2 ' 7 9 6 6 ' 4 ' 4 6 9 6 6 ' 4 ' 4 9 6 6 ' 4 6 ' 4 9 6 6 ' 4 6 $ 9 6 6 ' 4 6 ' 4 9 6 6 ' 4 ' 4 6 9 6 6 ' 4 6 ' $ 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 9 6 6 ' 4 ' 0 9 6 6 ' 4 ' 4 9 6 6 1 & & . 9 6 6 ' 4 9 6 6 1 & ' 4 9 6 6 ' 4 ' 0 9 6 6 & . ' 4 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 9 6 6 ' 4 ' 0 9 6 6 ' 4 ' 4 9 6 6 1 & ' 4 9 6 6 1 & 1 & 9 6 6 1 & 9 ' ' 4 9 ' ' $ $ 9 ' ' $ $ 9 ' ' & . $ % $ 5 $6 9 ' ' 4 1 & $ 9 6 6 ' 4 ' 0 9 6 6 ' 4 ' 4 9 6 6 1 & ' 4 9 6 6 ' 4 & . 9 6 6 1 & ' 4 9 6 6 ' 4 ' 0 9 6 6 ' 4 9 ' ' 6 3 ' 6 $ 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q ' 4 ' 4 9 6 6 1 & ' 4 9 6 6 ' 4 ' 0 9 6 6 ' 4 1 & 9 6 6 1 & 1 & 9 6 6 & . ( 1 & 9 ' ' 4 $ $ 9 ' ' 4 $ & . 9 ' ' 9 ' ' 9 ' ' 4 6 2 ' 7 9 ' ' ' 4 9 6 6 1 & ' 4 9 6 6 ' 4 ' 0 9 6 6 ' 4 ' 4 9 6 6 & . ' 0 9 6 6 ' 4 ' 4 9 6 6 1 & ' 4 9 6 6 6 $ ) 5 2 1 7 6 , ' ( % $ & . 6 , ' (
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 16 10202006-l0sm-feyt 3 electrical characteristics this chapter contains speed grade definition, ac timing parameter and odt tables. 3.1 absolute maximum ratings attention: stresses greater than those listed under ?abs olute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functi onal operation of the device at these or any other conditions above those indicated in the operational sect ions of this specification is not implied. exposure to absolute maximum rating conditions fo r extended periods may affect reliability. table 8 absolute maximum ratings table 9 environmental requirements symbol parameter rating unit note min. max. v dd voltage on v dd pin relative to v ss ?1.0 +2.3 v 1) 1) when v dd and v ddq and v ddl are less than 500 mv; v ref may be equal to or less than 300 mv. v ddq voltage on v ddq pin relative to v ss ?0.5 +2.3 v v ddl voltage on v ddl pin relative to v ss ?0.5 +2.3 v v in , v out voltage on any pin relative to v ss ?0.5 +2.3 v parameter symbol values unit note min. max. operating temperature (ambient) t opr 0+55 q c 1) 1) the component maximum case temperature (tcase) shall not e xceed the value specified in the ddr2 dram component specification. storage temperature t stg ? 50 +100 q c 2) 2) storage temperature is the case surface temperature on the center/top side of the dram. barometric pressure (operating & storage) pbar +69 +105 kpa 3) 3) up to 3000 m. operating humidity (relative) h opr 10 90 % storage humidity (without condensation) h stg 595%
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 17 10202006-l0sm-feyt table 10 dram component operating temperature range 3.2 dc operating conditions table 11 supply voltage levels an d dc operating conditions symbol parameter rating unit note min. max. t case operating temperature 0 95 c 1)2)3)4) 1) operating temperature is the case surface te mperature on the center / top side of the dram. 2) the operating temperature range are the temperatures where al l dram specification will be supported. during operation, the dr am case temperature must be maintained between 0 - 95 c under all other specification parameters. 3) above 85 q c the auto-refresh command interval has to be reduced to t refi = 3.9 p s 4) when operating this product in the 85 c to 95 c t case temperature range, the high temperature self refresh has to be enabled by setting emr(2) bit a7 to ?1?. when the high temperatur e self refresh is enabled there is an increase of i dd6 by approximately 50% parameter symbol values unit note min. typ. max. device supply voltage v dd 1.7 1.8 1.9 v output supply voltage v ddq 1.7 1.8 1.9 v 1) 1) under all conditions, v ddq must be less than or equal to v dd input reference voltage v ref 0.49 u v ddq 0.5 u v ddq 0.51 u v ddq v 2) 2) peak to peak ac noise on v ref may not exceed 2% v ref (dc). v ref is also expected to track noise in v ddq . spd supply voltage v ddspd 1.7 ? 3.6 v dc input logic high v ih(dc) v ref +0.125 ? v ddq +0.3 v dc input logic low v il (dc )? 0.30 ? v ref ?0.125 v in / output leakage current i l ? 5 ? 5 p a 3) 3) input voltage for any connector pin under test of 0 v d v in d v ddq + 0.3 v; all other pins at 0 v. current is per pin
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 18 10202006-l0sm-feyt 3.3 speed grade definitions table 12 speed grade definition speed grade ddr2?800d ddr2?800e unit note qag sort name ?25f ?2.5 cas-rcd-rp latencies 5?5?5 6?6?6 t ck parameter symbol min. max. min. max. ? clock period @ cl = 3 t ck 5858ns 1)2)3)4) @ cl = 4 t ck 3.75 8 3.75 8 ns 1)2)3)4) @ cl = 5 t ck 2.5838ns 1)2)3)4) @ cl = 6 t ck 2.5 8 2.5 8 ns 1)2)3)4) row active time t ras 40 70k 40 70k ns 1)2)3)4)5)7) row cycle time t rc 57.5 ? 60 ? ns 1)2)3)4) ras-cas-delay t rcd 12.5 ? 15 ? ns 1)2)3)4) row precharge time t rp 12.5 ? 15 ? ns 1)2)3)4)
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 19 10202006-l0sm-feyt table 13 speed grade definition 1) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. 2) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the crosspoint when in differential strobe mode. 3) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq 4) the output timing reference voltage level is v tt . 5) t ras.max is calculated from the maximum amount of time a ddr2 devic e can operate without a refresh command which is equal to 9 x t refi . 6) for products released before 01-09-2007. 7) products released after 01-09-2007 can support t ras.min = 40 ns for all ddr2 speed sort. speed grade ddr2?667c ddr2?667d ddr2?533c unit note qag sort name ?3 ?3s ?3.7 cas-rcd-rp latencies t ck 4?4?4 5?5?5 4?4?4 parameter ? symbol min. max. min. max. min. max. clock period @ cl = 3 t ck 585858ns 1)2)3)4) @ cl = 4 t ck 383.7583.758ns 1)2)3)4) @ cl = 5 t ck 38383.758ns 1)2)3)4) row active time t ras 40 70k 40 70k 40 70k ns 1)2)3)4)5)7) row cycle time t rc 57 ? 60 ? 60 ? ns 1)2)3)4) ras-cas-delay t rcd 12 ? 15 ? 15 ? ns 1)2)3)4) row precharge time t rp 12 ? 15 ? 15 ? ns 1)2)3)4)
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 20 10202006-l0sm-feyt 3.4 component ac timing parameters table 14 dram component timing parameter by speed grade - ddr2?800 and ddr2?667 parameter symbol ddr2?800 ddr2?667 unit note 1)2)3 )4)5)6)7) min. max. min. max. cas to cas command delay t ccd 2?2?nck average clock high pulse width t ch.avg 0.48 0.52 0.48 0.52 t ck.avg 9)10) average clock period t ck.avg 2500 8000 3000 8000 ps cke minimum pulse width ( high and low pulse width) t cke 3?3?nck 11) average clock low pulse width t cl.avg 0.48 0.52 0.48 0.52 t ck.avg 9)10) auto-precharge write recovery + precharge time t dal wr + t nrp ?wr+ t nrp ?nck 12)13) minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck .avg + t ih ?? t is + t ck .avg + t ih ?? ns dq and dm input hold time t dh.base 125 ?? 175 ?? ps 14)18)19) dq and dm input pulse width for each input t dipw 0.35 ? 0.35 ? t ck.avg dqs input high pulse width t dqsh 0.35 ? 0.35 ? t ck.avg dqs input low pulse width t dqsl 0.35 ? 0.35 ? t ck.avg dqs-dq skew for dqs & associated dq signals t dqsq ? 200 ? 240 ps 15) dqs latching rising transition to associated clock edges t dqss ? 0.25 + 0.25 ? 0.25 + 0.25 t ck.avg 16) dq and dm input setup time t ds.base 50 ?? 100 ?? ps 17)18)19) dqs falling edge hold time from ck t dsh 0.2 ? 0.2 ? t ck.avg 16) dqs falling edge to ck setup time t dss 0.2 ? 0.2 ? t ck.avg 16) ck half pulse width t hp min( t ch.abs , t cl.abs ) __ min( t ch.abs , t cl.abs ) __ ps 20) data-out high-impedance time from ck / ck t hz ? t ac.max ? t ac.max ps 8)21) address and control input hold time t ih.base 250 ? 275 ? ps 22)24) control & address input pulse width for each input t ipw 0.6 ? 0.6 ? t ck.avg address and control input setup time t is.base 175 ? 200 ? ps 23)24) dq low impedance time from ck/ck t lz.dq 2x t ac.min t ac.max 2x t ac.min t ac.max ps 8)21) dqs/dqs low-impedance time from ck / ck t lz.dqs t ac.min t ac.max t ac.min t ac.max ps 8)21) mrs command to odt update delay t mod 0 12 0 12 ns 34) mode register set command cycle time t mrd 2?2?nck
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 21 10202006-l0sm-feyt 1) v ddq = 1.8 v 0.1v; v dd = 1.8 v 0.1 v. 2) timing that is not specified is ille gal and after such an event, in order to guarantee proper operation, the dram must be pow ered down and then restarted through the specified initializa tion sequence before normal operation can continue. 3) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. 4) the ck / ck input reference level (for timing reference to ck / ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the crosspoint when in differential strobe mode. 5) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 6) the output timing reference voltage level is v tt . 7) new units, ? t ck.avg ? and ?nck?, are introduced in ddr2?667 and ddr2?800. unit ? t ck.avg ? represents the actual t ck.avg of the input clock under operation. unit ?nck? represents one clock cycle of the i nput clock, counting the actual clock edges. note that in ddr2?4 00 and ddr2?533, ? t ck ? is used for both concepts. example: t xp = 2 [nck] means; if power down exit is registered at tm, an active command may be registered at tm + 2, even if (tm + 2 - tm) is 2 x t ck.avg + t err.2per(min) . ocd drive mode output delay t oit 0 12 0 12 ns 34) dq/dqs output hold time from dqs t qh t hp ? t qhs ? t hp ? t qhs ?ps 25) dq hold skew factor t qhs ? 300 ? 340 ps 26) average periodic refresh interval t refi ?7.8?7.8 p s 27)28) ?3.9?3.9 p s 27)29) auto-refresh to active/auto-refresh command period t rfc 105 ? 105 ? ns 30) read preamble t rpre 0.9 1.1 0.9 1.1 t ck.avg 31)32) read postamble t rpst 0.4 0.6 0.4 0.6 t ck.avg 31)33) precharge-all (4 banks) command period t rp t rp ? t rp ?ns active to active command period for 1kb page size products t rrd 7.5 ? 7.5 ? ns 34) active to active command period for 2kb page size products t rrd 10 ? 10 ? ns 34) internal read to precharge command delay t rtp 7.5 ? 7.5 ? ns 34) write preamble t wpre 0.35 ? 0.35 ? t ck.avg write postamble t wpst 0.4 0.6 0.4 0.6 t ck.avg write recovery time t wr 15 ? 15 ? ns 34) internal write to read command delay t wtr 7.5 ? 7.5 ? ns 34)35) exit power down to read command t xard 2?2?nck exit active power-down mode to read command (slow exit, lower power) t xards 8 ? al ? 7 ? al ? nck exit precharge power-down to any valid command (other than nop or deselect) t xp 2?2?nck exit self-refresh to a non-read command t xsnr t rfc +10 ? t rfc +10 ? ns 34) exit self-refresh to read command t xsrd 200 ? 200 ? nck write command to dqs associated clock edges wl rl ? 1 rl?1 nck parameter symbol ddr2?800 ddr2?667 unit note 1)2)3 )4)5)6)7) min. max. min. max.
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 22 10202006-l0sm-feyt 8) when the device is operated with input clock jitter, this parameter needs to be derated by the actual t err(6-10per) of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2?667 sdram has t err(6-10per).min = ? 272 ps and t err(6- 10per).max = + 293 ps, then t dqsck.min(derated) = t dqsck.min ? t err(6-10per).max = ? 400 ps ? 293 ps = ? 693 ps and t dqsck.max(derated) = t dqsck.max ? t err(6-10per).min = 400 ps + 272 ps = + 672 ps. similarly, t lz.dq for ddr2?667 derates to t lz.dq.min(derated) = - 900 ps ? 293 ps = ? 1193 ps and t lz.dq.max(derated) = 450 ps + 272 ps = + 722 ps. (caution on the min/max usage!) 9) input clock jitter spec parameter. the jitter specified is a random ji tter meeting a gaussian distribution. 10) these parameters are specified per their average values. 11) t cke.min of 3 clocks means cke must be registered on three consecutive po sitive clock edges. cke must rema in at the valid input level t he entire time it takes to achieve the 3 cloc ks of registration. thus, after any cke trans ition, cke may not transition from its v alid level during the time period of t is + 2 x t ck + t ih . 12) dal = wr + ru{ t rp (ns) / t ck (ns)}, where ru stands for round up. wr refers to the twr parameter stored in the mrs. for t rp , if the result of the division is not already an integer, round up to the next highest integer. t ck refers to the application clock period. example: for ddr2?533 at t ck = 3.75 ns with t wr programmed to 4 clocks. t dal = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 13) t dal.nck = wr [nck] + t nrp.nck = wr + ru{ t rp [ps] / t ck.avg [ps] }, where wr is the value programmed in the emr. 14) input waveform timing t dh with differential data strobe enabled mr[bit10] = 0, is refe renced from the differential data strobe crosspoint to the input signal crossing at the v ih.dc level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the v il.dc level for a rising signal applied to the device under test. dqs, dqs signals must be monotonic between v il.dc.max and v ih.dc.min . see figure 4 . 15) t dqsq : consists of data pin skew and output pattern effects, and p-c hannel to n-channel variation of the output drivers as well as o utput slew rate mismatch between dqs / dqs and associated dq in any given cycle. 16) these parameters are measured from a data strobe signal ((l/u/r)dqs / dqs ) crossing to its respec tive clock signal (ck / ck ) crossing. the spec values are not affected by t he amount of clock jitter applied (i.e. t jit.per , t jit.cc , etc.), as these are relative to the clock signal crossing. that is, these param eters should be met whether clock jitter is present or not. 17) input waveform timing t ds with differential data strobe enabled mr[bit10] = 0, is re ferenced from the input signal crossing at the v ih.ac level to the differential data strobe crosspoint for a ri sing signal, and from the inpu t signal crossing at the v il.ac level to the differential data strobe crosspoint for a falling signal appli ed to the device under test. dqs, dq s signals must be monotonic between v il(dc)max and v ih(dc)min . see figure 4 . 18) if t ds or t dh is violated, data corruption may occur and the data must be re -written with valid data before a valid read can be executed. 19) these parameters are measured from a data signal ((l/u)dm, (l/u )dq0, (l/u)dq1, etc.) transition edge to its respective data strobe signal ((l/u/r)dqs / dqs ) crossing. 20) t hp is the minimum of the absolute hal f period of the actual input clock. t hp is an input parameter but not an input specification parameter. it is used in conjunction with t qhs to derive the dram output timing t qh . the value to be used for t qh calculation is determined by the following equation; t hp = min ( t ch.abs , t cl.abs ), where, t ch.abs is the minimum of the actual instantaneous clock high time; t cl.abs is the minimum of the actual in stantaneous clock low time. 21) t hz and t lz transitions occur in the same access time as valid data trans itions. these parameters are referenced to a specific voltage lev el which specifies when the device output is no longer driving ( t hz ), or begins driving ( t lz ) . 22) input waveform timing is referenced from the input signal crossing at the v il.dc level for a rising signal and v ih.dc for a falling signal applied to the device under test. see figure 5 . 23) input waveform timing is referenced from the input signal crossing at the v ih.ac level for a rising signal and v il.ac for a falling signal applied to the device under test. see figure 5 . 24) these parameters are measured from a comm and/address signal (cke, cs, ras, cas, we, odt, ba0, a0, a1, etc.) transition edge to its respective clock signal (ck / ck ) crossing. the spec values are not affect ed by the amount of cl ock jitter applied (i.e. t jit.per , t jit.cc , etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. that is, these paramet ers should be met whether clock jitter is present or not. 25) t qh = t hp ? t qhs , where: t hp is the minimum of the absolute half period of the actual input clock; and t qhs is the specification value under the max column. {the less half-pulse width distortion present, the larger the t qh value is; and the larger the valid data eye will be.} examples: 1) if the system provides t hp of 1315 ps into a ddr2?667 sdram, the dram provides t qh of 975 ps minimum. 2) if the system provides t hp of 1420 ps into a ddr2?667 sdram, the dram provides t qh of 1080 ps minimum. 26) t qhs accounts for: 1) the pulse duration distortion of on-chip clock circuits, which represents how well the actual t hp at the input is transferred to the output; and 2) the worst case push-out of dq s on one transition followed by the worst case pull-in of dq on the next transition, both of which are independent of each other, due to da ta pin skew, output pattern effects, and pchannel to n-channe l variation of the output drivers. 27) the auto-refresh command interval has be reduced to 3.9 s when operating the ddr2 dram in a temperature range between 85 q c and 95 q c. 28) 0 ? d t case d 85 q c. 29) 85 q c t case d 95 q c. 30) a maximum of eight refresh commands can be posted to any giv en ddr2 sdram, meaning that the maximum absolute interval betwe en any refresh command and the next refresh command is 9 x t refi .
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 23 10202006-l0sm-feyt 31) t rpst end point and t rpre begin point are not referenced to a specific voltage leve l but specify when the device output is no longer driving ( t rpst ), or begins driving ( t rpre ). figure 3 shows a method to calculate these point s when the device is no longer driving ( t rpst ), or begins driving ( t rpre ) by measuring the signal at two different voltages. the actual voltage measurement points are not critical as long as the calculation is consistent. 32) when the device is operated with i nput clock jitter, this parameter needs to be derated by the actual t jit.per of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2?667 sdram has t jit.per.min = ? 72 ps and t jit.per.max = + 93 ps, then t rpre.min(derated) = t rpre.min + t jit.per.min = 0.9 x t ck.avg ? 72 ps = + 2178 ps and t rpre.max(derated) = t rpre.max + t jit.per.max = 1.1 x t ck.avg + 93 ps = + 2843 ps. (caution on the min/max usage!). 33) when the device is operated with i nput clock jitter, this parameter needs to be derated by the actual t jit.duty of the input clock. (output deratings are relative to the sdram input clock.) for ex ample, if the measured jitter into a ddr2?667 sdram has t jit.duty.min = ? 72 ps and t jit.duty.max = + 93 ps, then t rpst.min(derated) = t rpst.min + t jit.duty.min = 0.4 x t ck.avg ? 72 ps = + 928 ps and t rpst.max(derated) = t rpst.max + t jit.duty.max = 0.6 x t ck.avg + 93 ps = + 1592 ps. (caution on the min/max usage!). 34) for these parameters, the ddr2 sdram device is characterized and verified to support t nparam = ru{ t param / t ck.avg }, which is in clock cycles, assuming all input cl ock jitter specifications are satisfied. for example, the device will support t nrp = ru{ t rp / t ck.avg }, which is in clock cycles, if all input clock jitter specifications are met. this means: for ddr2?667 5?5?5, of which t rp = 15 ns, the device will support t nrp = ru{ t rp / t ck.avg } = 5, i.e. as long as the input cloc k jitter specifications are met, prechar ge command at tm and active command at tm + 5 is valid even if (tm + 5 - tm) is less than 15 ns due to input clock jitter. 35) t wtr is at lease two clocks (2 x t ck ) independent of operation frequency. 36) this timing parameter is relaxed than industry standard
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 24 10202006-l0sm-feyt table 15 dram component timing parameter by speed grade - ddr2?533 parameter symbol ddr2?533 unit notes 1)2)3)4)5) 6) min. max. cas a to cas b command period t ccd 2? t ck ck, ck high-level width t ch 0.45 0.55 t ck cke minimum high and low pulse width t cke 3? t ck ck, ck low-level width t cl 0.45 0.55 t ck auto-precharge write recovery + precharge time t dal wr + t rp ? t ck 7) minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck + t ih ?? ns 8) dq and dm input hold time (differential data strobe) t dh.base 225 ?? ps 9) dq and dm input hold time (single ended data strobe) t dh1.base ?25 ? ps 10) dq and dm input pulse width (each input) t dipw 0.35 ? t ck dqs input high pulse width (write cycle) t dqsh 0.35 ? t ck dqs input low pulse width (write cycle) t dqsl 0.35 ? t ck dqs-dq skew (for dqs & associated dq signals) t dqsq ? 300 ps 10) write command to 1st dqs latching transition t dqss ? 0.25 + 0.25 t ck dq and dm input setup time (differential data strobe) t ds.base 100 ? ps 10) dq and dm input setup time (single ended data strobe) t ds1.base ?25 ? ps 10) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? t ck dqs falling edge to ck setup time (write cycle) t dss 0.2 ? t ck clock half period t hp min. ( t cl, t ch ) 11) data-out high-impedance time from ck / ck t hz ? t ac.max ps 12) address and control input hold time t ih.base 375 ? ps 10) address and control input pulse width (each input) t ipw 0.6 ? t ck address and control input setup time t is.base 250 ? ps 10) dq low-impedance time from ck / ck t lz(dq) 2 u t ac.min t ac.max ps 13) dqs low-impedance from ck / ck t lz(dqs) t ac.min t ac.max ps 13) mrs command to odt update delay t mod 012ns mode register set command cycle time t mrd 2? t ck ocd drive mode output delay t oit 012ns
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 25 10202006-l0sm-feyt 1) v ddq = 1.8 v 0.1v; v dd = 1.8 v 0.1 v. 2) timing that is not specified is ille gal and after such an event, in order to guarantee proper operation, the dram must be pow ered down and then restarted through the specified initializa tion sequence before normal operation can continue. 3) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. 4) the ck / ck input reference level (for timing reference to ck / ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the crosspoint when in differential strobe mode. 5) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 6) the output timing reference voltage level is v tt . 7) for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mr. 8) the clock frequency is allowed to change during self-refresh mode or precharge power-down mode. 9) for timing definition, refer to the component data sheet. 10) consists of data pin skew and output pattern effects, and p-ch annel to n-channel variation of the output drivers as well as output slew rate mis-match between dqs / dqs and associated dq in any given cycle. data output hold time from dqs t qh t hp ? t qhs ? data hold skew factor t qhs ? 400 ps average periodic refresh interval t refi ?7.8 p s 13)14) average periodic refresh interval t refi ?3.9 p s 15)17) auto-refresh to active/auto-refresh command period t rfc 105 ? ns 16) precharge-all (4 banks) command period t rp t rp ?ns read preamble t rpre 0.9 1.1 t ck 13) read postamble t rpst 0.40 0.60 t ck 13) active bank a to active bank b command period for 1 kb page size t rrd 7.5 ? ns 13)17) active bank a to active bank b command period for 2 kb page size t rrd 10 ? ns 15)21) internal read to precharge command delay t rtp 7.5 ? ns write preamble t wpre 0.25 ? t ck write postamble t wpst 0.40 0.60 t ck 18) write recovery time for write without auto-precharge t wr 15 ? ns internal write to read command delay t wtr 7.5 ? ns 19) exit power down to any valid command (other than nop or deselect) t xard 2? t ck 20) exit active power-down mode to read command (slow exit, lower power) t xards 6 ? al ? t ck 20) exit precharge power-down to any valid command (other than nop or deselect) t xp 2? t ck exit self-refresh to non-read command t xsnr t rfc +10 ? ns exit self-refresh to read command t xsrd 200 ? t ck write recovery time for write with auto- precharge wr t wr / t ck t ck 21) parameter symbol ddr2?533 unit notes 1)2)3)4)5) 6) min. max.
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 26 10202006-l0sm-feyt 11) min ( t cl , t ch ) refers to the smaller of the actual clock low time and the ac tual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t cl and t ch ). 12) the t hz , t rpst and t lz , t rpre parameters are referenced to a specific voltage level, wh ich specify when the device output is no longer driving ( t hz, t rpst ), or begins driving ( t lz, t rpre ). t hz and t lz transitions occur in the same access ti me windows as valid data transitions.these parameters are verified by design and characteri zation, but not subject to production test. 13) the auto-refresh command interval has be reduced to 3.9 s when operating the ddr2 dram in a temperature range between 85 q c and 95 q c. 14) 0 ? d t case d 85 q c. 15) 85 q c t case d 95 q c. 16) a maximum of eight refresh commands can be posted to any given ddr2 sdram, meaning that the maximum absolute interval betwee n any refresh command and the next refresh command is 9 x t refi . 17) the t rrd timing parameter depends on the page size of the dram organization. 18) the maximum limit for the t wpst parameter is not a device limit. the device operates wi th a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 19) minimum t wtr is two clocks when operating the ddr2-sdram at frequencies d0+ z. 20) user can choose two different active pow er-down modes for additional power saving via mrs address bit a12. in ?standard acti ve power- down mode? (mr, a12 = ?0?) a fast power-down exit timing t xard can be used. in ?low active power-down mode? (mr, a12 =?1?) a slow power-down exit timing t xards has to be satisfied. 21) wr must be programmed to fulfill the minimum requirement for the t wr timing parameter, where wr min [cycles] = t wr (ns)/ t ck (ns) rounded up to the next integer value. t dal = wr + ( t rp / t ck ). for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mrs. figure 3 method for calculating transitions and endpoint

hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 27 10202006-l0sm-feyt figure 4 differential input waveform timing t ds and t dh figure 5 differential input waveform timing t ls and t lh 9 ''4 9 ,+$&0,1 9 ,+'&0,1 9 5() 9 ,/'&0$; 9 ,/$&0$; 9 66 03(7 w '6 w '+ w '6 w '+ '46 '46 '4 9 ''4 9 ,+$&0,1 9 ,+'&0,1 9 5() 9 ,/'&0$; 9 ,/$&0$; 9 66 03(7 w ,6 w ,+ w ,6 w ,+ &. &. &0' $gguhvv
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 28 10202006-l0sm-feyt 3.5 odt ac electrical characteristics this chapter describes the odt ac electrical characteristics. table 16 odt ac characteristics and operating conditions for ddr2-667 , ddr2-800 symbol parameter / condition values unit note min. max. t aond odt turn-on delay 2 2 n ck 1) 1) new units, ? t ck.avg ? and ? n ck ?, are introduced in ddr2-667 and ddr2-800 unit ? t ck.avg ? represents the actual t ck.avg of the input clock under operation. unit ? n ck ? represents one clock cycle of the input clock, count ing the actual clock edges. note that in ddr2-400 and ddr2-533, ? t ck ? is used for both concepts. example: t xp = 2 [ n ck ] means; if power down exit is registered at t m , an active command may be registered at t m + 2, even if ( t m + 2 - t m ) is 2 x t ck.avg + t err.2per(min) . t aon odt turn-on t ac.min t ac.max +0.7ns ns 1)2) 2) odt turn on time min is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max is w hen the odt resistance is fully on. both are measured from t aond , which is interpreted differently per speed bin. for ddr2-667/800 t aond is 2 clock cycles after the clock edge that registered a first odt high counting the actual input clock edges. t aonpd odt turn-on (power-down modes) t ac.min + 2 ns 2 t ck + t ac.max + 1 ns ns 1) t aofd odt turn-off delay 2.5 2.5 n ck 1) t aof odt turn-off t ac.min t ac.max +0.6ns ns 1)3) 3) odt turn off time min is when the device starts to turn off od t resistance. odt turn off time max is when the bus is in high impedance. both are measured from t aofd , which is interpreted differently per speed bin. for ddr2-667/800, if t ck(avg) = 3 ns is assumed, t aofd is 1.5 ns (= 0.5 x 3 ns) after the se cond trailing clock edge counting from the cl ock edge that registered a first odt low and by counting the actual input clock edges. t aofpd odt turn-off (power-down modes) t ac.min + 2 ns 2.5 t ck + t ac.max +1ns ns 1) t anpd odt to power down mode entry latency 3 ? n ck 1) t axpd odt power down exit latency 8 ? n ck 1)
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 29 10202006-l0sm-feyt table 17 odt ac characteristics and operating conditions for ddr2-533 symbol parameter / condition values unit note min. max. t aond odt turn-on delay 2 2 t ck t aon odt turn-on t ac.min t ac.max + 1 ns ns 1) 1) odt turn on time min. is when the devic e leaves high impedance and odt re sistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measured from t aond , which is interpreted differently per speed bin. for ddr2-400/533, t aond is 10 ns (= 2 x 5 ns) after the clock edge that registered a first odt high if t ck = 5 ns. t aonpd odt turn-on (power-down modes) t ac.min + 2 ns 2 t ck + t ac.max + 1 ns ns t aofd odt turn-off delay 2.5 2.5 t ck t aof odt turn-off t ac.min t ac.max + 0.6 ns ns 2) 2) odt turn off time min. is when the device starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance. both are measured from t aofd . both are measured from t aofd , which is interpreted differently per speed bin. for ddr2-400/533, t aofd is 12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first odt high if t ck = 5 ns. t aofpd odt turn-off (power-down modes) t ac.min + 2 ns 2.5 t ck + t ac.max + 1 ns ns t anpd odt to power down mode entry latency 3 ? t ck t axpd odt power down exit latency 8 ? t ck
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 30 10202006-l0sm-feyt 3.6 i dd specifications and conditions list of tables defining i dd specifications and conditions. table 18 i dd measurement conditions parameter symbol note 1)2) 3)4)5) operating current 0 one bank active - precharge; t ck = t ck.min , t rc = t rc.min , t ras = t ras.min , cke is high, cs is high between valid commands. address and control inputs are switching, databus inputs are switching. i dd0 operating current 1 one bank active - read - precharge; i out = 0 ma, bl = 4, t ck = t ck.min , t rc = t rc.min , t ras = t ras.min , t rcd = t rcd.min , al = 0, cl = cl min ; cke is high, cs is high between valid commands. address and control inputs are switching, databus inputs are switching. i dd1 6) precharge standby current all banks idle; cs is high; cke is high; t ck = t ck.min ; other control and address inputs are switching, databus inputs are switching. i dd2n precharge power-down current other control and address inputs are st able, data bus inputs are floating. i dd2p precharge quiet standby current all banks idle; cs is high; cke is high; t ck = t ck.min ; other control and address inputs are stable, data bus inputs are floating. i dd2q active standby current burst read: all banks open; continuous burst reads; bl = 4; al = 0, cl = cl min ; t ck = t ck.min ; t ras = t ras.max , t rp = t rp.min ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i out = 0 ma. i dd3n active power-down current all banks open; t ck = t ck.min , cke is low; other control and addres s inputs are stable, data bus inputs are floating. mrs a12 bit is se t to low (fast power-down exit); i dd3p(0) active power-down current all banks open; t ck = t ck.min , cke is low; other control and address inputs are stable, data bus inputs are floating. mrs a12 bit is set to high (slow power-down exit); i dd3p(1) operating current - burst read all banks open; continuous burst re ads; bl = 4; al = 0, cl = cl min ; t ck = t ckmin ; t ras = t rasmax ; t rp = t rpmin ; cke is high, cs is high between valid co mmands; address inputs are switching; data bus inputs are switching; i out = 0ma. i dd4r 6) operating current - burst write all banks open; continuous burst wr ites; bl = 4; al = 0, cl = cl min ; t ck = t ck.min ; t ras = t ras.max. , t rp = t rp.max ; cke is high, cs is high between valid commands. address inputs are switching; data bus in puts are switching; i dd4w burst refresh current t ck = t ck.min ., refresh command every t rfc = t rfc.min interval, cke is high, cs is high between valid commands, other control and address inputs ar e switching, data bus inputs are switching. i dd5b distributed refresh current t ck = t ck.min. , refresh command every t rfc = t refi interval, cke is low and cs is high between valid commands, other control and address inputs ar e switching, data bus inputs are switching. i dd5d
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 31 10202006-l0sm-feyt table 19 definitions for i dd self-refresh current cke d 0.2 v; external clock off, ck and ck at 0 v; other control and address inputs are floating, data bus inputs are floating. i dd6 current values are guaranteed up to t case of 85 q c max. i dd6 all bank interleave read current all banks are being interleaved at minimum t rc without violating t rrd using a burst length of 4. control and address bus inputs are stable during deselects. i out = 0 ma. i dd7 6) 1) v ddq = 1.8 v r 0.1 v; v dd = 1.8 v r 0.1 v 2) i dd specifications are tested after t he device is properly initialized and i dd parameter are specified with odt disabled. 3) definitions for i dd see table 19 4) for two rank modules: all active current measurements in the same i dd current mode. the other rank is in i dd2p precharge power-down mode. 5) for details and notes see the relevant qimonda component data sheet. 6) i dd1 , i dd4r and i dd7 current measurements are defined with the outputs disabled ( i out = 0 ma). to achieve this on module level the output buffers can be disabled using an emrs(1) (extended m ode register command) by setting a12 bit to high. parameter description low v in d v il(ac).max , high is defined as v in t v ih(ac).min stable inputs are stable at a high or low level. floating inputs are v ref = v ddq /2 switching inputs are changing between high and low ever y other clock (once per 2 cycles) for address and control signals, and inputs changing between high and lo w every other data transfer (once per cycle) for dq signals not including mask or strobes. parameter symbol note 1)2) 3)4)5)
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 32 10202006-l0sm-feyt table 20 i dd specification for hys[64/72] t[32/64/128][0/9]xxeu-25f-b2 product type hys64t32000eu?25f?b2 hys64t32900eu?25f?b2 hys64t64000eu?25f?b2 hys64t64900eu?25f?b2 hys72t64000eu?25f?b2 hys72t64900eu?25f?b2 hys64t128020eu?25f?b2 hys64t128920eu?25f?b2 hys72t128020eu?25f?b2 hys72t128920eu?25f?b2 unit note 1) 1) calculated values from component data. odt disabled. i dd1, i dd4r and i dd7 are defined with the outputs disabled. organization 256mb 512mb 512mb 1gb 1gb 1 rank 1 rank 1 rank 2 ranks 2 ranks u 64 u 64 u 72 u 64 u 72 -25f -25f -25f -25f -25f symbol max max max max. max. i dd0 420 672 756 740 840 ma 2) 2) the other rank is in i dd2p precharge power-down current mode i dd1 480 800 900 870 980 ma 2) i dd2n 204 408 459 820 920 ma 3) 3) both ranks are in the same i dd current mode i dd2p 36 72 81 140 160 ma 3) i dd2q 180 360 405 720 810 ma 3) i dd3n 240 480 540 960 1080 ma 3) i dd3p_0 (fast) 156 312 351 620 700 ma 3)4) 4) fast: mrs(12)=0 i dd3p_1 (slow) 52 104 117 210 230 ma 3)5) 5) slow: mrs(12)=1 i dd4r 720 1240 1395 1310 1480 ma 2) i dd4w 800 1240 1395 1310 1480 ma 2) i dd5b 580 1160 1305 1230 1390 ma 2) i dd5d 44 88 99 180 200 ma 3)6) 6) i dd5d and i dd6 values are for 0 q c d t case d 85 q c i dd6 36 72 81 144 162 ma 3)6) i dd7 1060 1360 1530 1430 1610 ma 2)
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 33 10202006-l0sm-feyt table 21 i dd specification for hys[64/72]t[32/64/128][0/9]xxeu-2.5-b2 product type hys64t32000eu?2.5?b2 hys64t32900eu?2.5?b2 hys64t64000eu?2.5?b2 hys64t64900eu?2.5?b2 hys72t64000eu?2.5?b2 hys72t64900eu?2.5?b2 hys64t128020eu?2.5?b2 hys64t128920eu?2.5?b2 hys72t128020eu?2.5?b2 hys72t128920eu?2.5?b2 unit note 1) 1) calculated values from component data. odt disabled. i dd1, i dd4r and i dd7 are defined with the outputs disabled. organization 256mb 512mb 512mb 1gb 1gb 1 rank 1 rank 1 rank 2 ranks 2 ranks u 64 u 64 u 72 u 64 u 72 -2.5 -2.5 -2.5 -2.5 -2.5 symbol max max max max. max. i dd0 400 640 720 710 800 ma 2) 2) the other rank is in i dd2p precharge power-down current mode i dd1 460 760 855 830 940 ma 2) i dd2n 204 408 459 820 920 ma 3) 3) both ranks are in the same i dd current mode i dd2p 36 72 81 140 160 ma 3) i dd2q 180 360 405 720 810 ma 3) i dd3n 240 480 540 960 1080 ma 3) i dd3p_0 (fast) 156 312 351 620 700 ma 3)4) 4) fast: mrs(12)=0 i dd3p_1 (slow) 52 104 117 210 230 ma 3)5) 5) slow: mrs(12)=1 i dd4r 720 1240 1395 1310 1480 ma 2) i dd4w 800 1240 1395 1310 1480 ma 2) i dd5b 580 1160 1305 1230 1390 ma 2) i dd5d 44 88 99 180 200 ma 3)6) 6) i dd5d and i dd6 values are for 0 q c d t case d 85 q c i dd6 36 72 81 144 162 ma 3)6) i dd7 1020 1280 1440 1350 1520 ma 2)
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 34 10202006-l0sm-feyt table 22 i dd specification for hys[64/72]t[32/64/128][0/9]xxeu-3-b2 product type hys64t32000eu?3?b2 hys64t32900eu?3?b2 hys64t64000eu?3?b2 hys64t64900eu?3?b2 hys72t64000eu?3?b2 hys72t64900eu?3?b2 hys64t128020eu?3?b2 hys64t128920eu?3?b2 hys72t128020eu?3?b2 hys72t128920eu?3?b2 unit note 1) 1) calculated values from component data. odt disabled. i dd1, i dd4r and i dd7 are defined with the outputs disabled. organization 256mb 512mb 512mb 1gb 1gb 1 rank 1 rank 1 rank 2 ranks 2 ranks u 64 u 64 u 72 u 64 u 72 -3 -3 -3 -3 -3 symbol max max max max. max. i dd0 380 600 675 670 760 ma 2) 2) the other rank is in i dd2p precharge power-down current mode i dd1 420 720 810 790 890 ma 2) i dd2n 180 360 405 720 810 ma 3) 3) both ranks are in the same i dd current mode i dd2p 36 72 81 140 160 ma 3) i dd2q 160 320 360 640 720 ma 3) i dd3n 200 400 450 800 900 ma 3) i dd3p_0 (fast) 132 264 297 530 590 ma 3)4) 4) fast: mrs(12)=0 i dd3p_1 (slow) 52 104 117 210 230 ma 3)5) 5) slow: mrs(12)=1 i dd4r 620 1040 1170 1110 1250 ma 2) i dd4w 680 1040 1170 1110 1250 ma 2) i dd5b 560 1120 1260 1190 1340 ma 2) i dd5d 44 88 99 180 200 ma 3)6) 6) i dd5d and i dd6 values are for 0 q c d t case d 85 q c i dd6 36 72 81 144 162 ma 3)6) i dd7 1008 1280 1440 1350 1520 ma 2)
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 35 10202006-l0sm-feyt table 23 i dd specification for hys[64/72]t[32/64/128][0/9]xxeu-3s-b2 product type hys64t32000eu?3s?b2 hys64t32900eu?3s?b2 hys64t64000eu?3s?b2 hys64t64900eu?3s?b2 hys72t64000eu?3s?b2 hys72t64900eu?3s?b2 hys64t128020eu?3s?b2 hys64t128920eu?3s?b2 hys72t128020eu?3s?b2 hys72t128920eu?3s?b2 unit note 1) 1) calculated values from component data. odt disabled. i dd1, i dd4r and i dd7 are defined with the outputs disabled. organization 256mb 512mb 512mb 1gb 1gb 1 rank 1 rank 1 rank 2 ranks 2 ranks u 64 u 64 u 72 u 64 u 72 -3s -3s 3s -3s -3s symbol max max max max. max. i dd0 360 568 639 640 720 ma 2) 2) the other rank is in i dd2p precharge power-down current mode i dd1 400 680 765 750 850 ma 2) i dd2n 180 360 405 720 810 ma 3) 3) both ranks are in the same i dd current mode i dd2p 36 72 81 140 160 ma 3) i dd2q 160 320 360 640 720 ma 3) i dd3n 200 400 450 800 900 ma 3) i dd3p_0 (fast) 132 264 297 530 590 ma 3)4) 4) fast: mrs(12)=0 i dd3p_1 (slow) 52 104 117 210 230 ma 3)5) 5) slow: mrs(12)=1 i dd4r 620 1040 1170 1110 1250 ma 2) i dd4w 680 1040 1170 1110 1250 ma 2) i dd5b 560 1120 1260 1190 1340 ma 2) i dd5d 44 88 99 180 200 ma 3)6) 6) i dd5d and i dd6 values are for 0 q c d t case d 85 q c i dd6 36 72 81 144 162 ma 3)6) i dd7 960 1216 1368 1290 1450 ma 2)
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 36 10202006-l0sm-feyt table 24 i dd specification for hys[64/72]t[32/64/128][0/9]xxeu-3.7-b2 product type hys64t32000eu?3.7?b2 hys64t32900eu?3.7?b2 hys64t64000eu?3.7?b2 hys64t64900eu?3.7?b2 hys72t64000eu?3.7?b2 hys72t64900eu?3.7?b2 hys64t128020eu?3.7?b2 hys64t128920eu?3.7?b2 hys72t128020eu?3.7?b2 hys72t128920eu?3.7?b2 unit note 1) 1) calculated values from component data. odt disabled. i dd1, i dd4r and i dd7 are defined with the outputs disabled. organization 256mb 512mb 512mb 1gb 1gb 1 rank 1 rank 1 rank 2 ranks 2 ranks u 64 u 64 u 72 u 64 u 72 -3.7 -3.7 -3.7 -3.7 -3.7 symbol max max max max. max. i dd0 320 520 585 590 670 ma 2) 2) the other rank is in i dd2p precharge power-down current mode i dd1 360 600 675 670 760 ma 2) i dd2n 152 304 342 610 680 ma 3) 3) both ranks are in the same i dd current mode i dd2p 36 72 81 140 160 ma 3) i dd2q 140 280 315 560 630 ma 3) i dd3n 172 344 387 690 770 ma 3) i dd3p_0 (fast) 112 224 252 450 500 ma 3)4) 4) fast: mrs(12)=0 i dd3p_1 (slow) 52 104 117 210 230 ma 3)5) 5) slow: mrs(12)=1 i dd4r 520 880 990 950 1070 ma 2) i dd4w 580 880 990 950 1070 ma 2) i dd5b 520 1040 1170 1110 1250 ma 2) idd5d 448899180200ma 3)6) 6) i dd5d and i dd6 values are for 0 q c d t case d 85 q c idd6 36 72 81 144 162 ma 3)6) idd7 920 1160 1305 1230 1390 ma 2)
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 37 10202006-l0sm-feyt 4 spd codes this chapter lists all hexadecimal byte values stored in the eeprom of the products described in this data sheet. spd stands for serial presence detect. all values with xx in the table are module specific bytes which are defined during production. list of spd code tables ? table 25 ?hys64t[32/64]x00eu-25f-b2? on page 37 ? table 26 ?hys[64/72]t[64/128]xx0eu-25f-b2? on page 42 ? table 27 ?hys64t[32/64]x00eu-2.5-b2? on page 47 ? table 28 ?hys[64/72]t[64/128]xx0eu-2.5-b2? on page 51 ? table 29 ?hys64t[32/64]x00eu-3-b2? on page 56 ? table 30 ?hys[64/72]t[64/128]xx0eu-3-b2? on page 60 ? table 31 ?hys64t[32/64]x00eu-3s-b2? on page 65 ? table 32 ?hys[64/72]t[64/128]xx0eu-3s-b2? on page 69 ? table 33 ?hys64t[32/64]x00eu-3.7-b2? on page 74 ? table 34 ?hys[64/72]t[64/128]xx0eu-3.7-b2? on page 78 table 25 hys64t[32/64]x00eu-25f-b2 product type hys64t32000eu?25f?b2 hys64t32900eu?25f?b2 hys64t64000eu?25f?b2 hys64t64900eu?25f?b2 organization 256mb 256mb 512mb 512mb u 64 u 64 u 64 u 64 1 rank ( u 16) 1 rank ( u 16) 1 rank ( u 8) 1 rank ( u 8) label code pc2? 6400u?555 pc2? 6400u?555 pc2? 6400u?555 pc2? 6400u?555 jedec spd revision rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex 0 programmed spd bytes in eeprom 80 80 80 80 1 total number of bytes in eeprom 08 08 08 08 2 memory type (ddr2) 08 08 08 08 3 number of row addresses 0d 0d 0e 0e 4 number of column addresses 0a 0a 0a 0a 5 dimm rank and stacking information 60 60 60 60 6 data width 40 40 40 40
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 38 10202006-l0sm-feyt 7 not used 00 00 00 00 8 interface voltage level 05 05 05 05 9 t ck @ cl max (byte 18) [ns] 25 25 25 25 10 t ac sdram @ cl max (byte 18) [ns] 40 40 40 40 11 error correction support (non-ecc, ecc) 00 00 00 00 12 refresh rate and type 82 82 82 82 13 primary sdram width 10 10 08 08 14 error checking sdram width 00 00 00 00 15 not used 00 00 00 00 16 burst length supported 0c 0c 0c 0c 17 number of banks on sdram device 04 04 04 04 18 supported cas latencies 70 70 70 70 19 dimm mechanical characteristics 01 01 01 01 20 dimm type information 02 02 02 02 21 dimm attributes 00 00 00 00 22 component attributes 07 07 07 07 23 t ck @ cl max -1 (byte 18) [ns] 25 25 25 25 24 t ac sdram @ cl max -1 [ns] 40 40 40 40 25 t ck @ cl max -2 (byte 18) [ns] 3d 3d 3d 3d 26 t ac sdram @ cl max -2 [ns] 50 50 50 50 27 t rp.min [ns] 32 32 32 32 28 t rrd.min [ns] 28 28 1e 1e 29 t rcd.min [ns] 32 32 32 32 30 t ras.min [ns] 2d 2d 2d 2d 31 module density per rank 40 40 80 80 product type hys64t32000eu?25f?b2 hys64t32900eu?25f?b2 hys64t64000eu?25f?b2 hys64t64900eu?25f?b2 organization 256mb 256mb 512mb 512mb u 64 u 64 u 64 u 64 1 rank ( u 16) 1 rank ( u 16) 1 rank ( u 8) 1 rank ( u 8) label code pc2? 6400u?555 pc2? 6400u?555 pc2? 6400u?555 pc2? 6400u?555 jedec spd revision rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 39 10202006-l0sm-feyt 32 t as.min and t cs.min [ns] 17 17 17 17 33 t ah.min and t ch.min [ns] 25 25 25 25 34 t ds.min [ns] 05 05 05 05 35 t dh.min [ns] 12 12 12 12 36 t wr.min [ns] 3c 3c 3c 3c 37 t wtr.min [ns] 1e 1e 1e 1e 38 t rtp.min [ns] 1e 1e 1e 1e 39 analysis characteristics 00 00 00 00 40 t rc and t rfc extension 30303030 41 t rc.min [ns] 39 39 39 39 42 t rfc.min [ns] 69 69 69 69 43 t ck.max [ns] 80 80 80 80 44 t dqsq.max [ns] 14 14 14 14 45 t qhs.max [ns] 1e 1e 1e 1e 46 pll relock time 00 00 00 00 47 t case.max delta / ' t 4r4w delta 56 56 50 50 48 psi(t-a) dram 7a 7a 7a 7a 49 ' t 0 (dt0) 7f7f5f5f 50 ' t 2n (dt2n, udimm) or ' t 2q (dt2q, rdimm) 3b 3b 3b 3b 51 ' t 2p (dt2p) 36 36 36 36 52 ' t 3n (dt3n) 2e 2e 2e 2e 53 ' t 3p.fast (dt3p fast) 5a5a5a5a 54 ' t 3p.slow (dt3p slow) 2a2a2a2a 55 ' t 4r (dt4r) / ' t 4r4w sign (dt4r4w) 68 68 5a 5a 56 ' t 5b (dt5b) 22 22 22 22 product type hys64t32000eu?25f?b2 hys64t32900eu?25f?b2 hys64t64000eu?25f?b2 hys64t64900eu?25f?b2 organization 256mb 256mb 512mb 512mb u 64 u 64 u 64 u 64 1 rank ( u 16) 1 rank ( u 16) 1 rank ( u 8) 1 rank ( u 8) label code pc2? 6400u?555 pc2? 6400u?555 pc2? 6400u?555 pc2? 6400u?555 jedec spd revision rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 40 10202006-l0sm-feyt 57 ' t 7 (dt7) 3d 3d 27 27 58 psi(ca) pll 00 00 00 00 59 psi(ca) reg 00 00 00 00 60 ' t pll (dtpll) 00000000 61 ' t reg (dtreg) / toggle rate 00 00 00 00 62 spd revision 12 12 12 12 63 checksum of bytes 0-62 52 52 37 37 64 manufacturer?s jedec id code (1) 7f 7f 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 7f 7f 66 manufacturer?s jedec id code (3) 7f 7f 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 00 72 module manufacturer location xx xx xx xx 73 product type, char 1 36 36 36 36 74 product type, char 2 34 34 34 34 75 product type, char 3 54 54 54 54 76 product type, char 4 33 33 36 36 77 product type, char 5 32 32 34 34 78 product type, char 6 30 39 30 39 79 product type, char 7 30 30 30 30 80 product type, char 8 30 30 30 30 81 product type, char 9 45 45 45 45 product type hys64t32000eu?25f?b2 hys64t32900eu?25f?b2 hys64t64000eu?25f?b2 hys64t64900eu?25f?b2 organization 256mb 256mb 512mb 512mb u 64 u 64 u 64 u 64 1 rank ( u 16) 1 rank ( u 16) 1 rank ( u 8) 1 rank ( u 8) label code pc2? 6400u?555 pc2? 6400u?555 pc2? 6400u?555 pc2? 6400u?555 jedec spd revision rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 41 10202006-l0sm-feyt 82 product type, char 10 55 55 55 55 83 product type, char 11 32 32 32 32 84 product type, char 12 35 35 35 35 85 product type, char 13 46 46 46 46 86 product type, char 14 42 42 42 42 87 product type, char 15 32 32 32 32 88 product type, char 16 20 20 20 20 89 product type, char 17 20 20 20 20 90 product type, char 18 20 20 20 20 91 module revision code 3x 0x 3x 0x 92 test program revision code xx xx xx xx 93 module manufacturing date year xx xx xx xx 94 module manufacturing date week xx xx xx xx 95 - 98 module serial number xx xx xx xx 99 - 127 not used 00 00 00 00 128 - 255 blank for customer use ff ff ff ff product type hys64t32000eu?25f?b2 hys64t32900eu?25f?b2 hys64t64000eu?25f?b2 hys64t64900eu?25f?b2 organization 256mb 256mb 512mb 512mb u 64 u 64 u 64 u 64 1 rank ( u 16) 1 rank ( u 16) 1 rank ( u 8) 1 rank ( u 8) label code pc2? 6400u?555 pc2? 6400u?555 pc2? 6400u?555 pc2? 6400u?555 jedec spd revision rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 42 10202006-l0sm-feyt table 26 hys[64/72]t[64/128]xx0eu-25f-b2 product type hys72t64000eu?25f?b2 hys72t64900eu?25f?b2 hys64t128020eu?25f?b2 hys64t128920eu?25f?b2 hys72t128020eu?25f?b2 hys72t128920eu?25f?b2 organization 512mb 512mb 1 gbyte 1 gbyte 1 gbyte 1 gbyte u 72 u 72 u 64 u 64 u 72 u 72 1 rank ( u 8) 1 rank ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) label code pc2? 6400e? 555 pc2? 6400e? 555 pc2? 6400u? 555 pc2? 6400u? 555 pc2? 6400e? 555 pc2? 6400e? 555 jedec spd revision rev. 1.2 rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hex hex 0 programmed spd bytes in eeprom 80 80 80 80 80 80 1 total number of bytes in eeprom 08 08 08 08 08 08 2 memory type (ddr2) 08 08 08 08 08 08 3 number of row addresses 0e 0e 0e 0e 0e 0e 4 number of column addresses 0a 0a 0a 0a 0a 0a 5 dimm rank and stacking information 60 60 61 61 61 61 6 data width 484840404848 7 not used 00 00 00 00 00 00 8 interface voltage level 05 05 05 05 05 05 9 t ck @ cl max (byte 18) [ns] 25 25 25 25 25 25 10 t ac sdram @ cl max (byte 18) [ns] 40 40 40 40 40 40 11 error correction support (non-ecc, ecc) 02 02 00 00 02 02 12 refresh rate and type 82 82 82 82 82 82 13 primary sdram width 08 08 08 08 08 08 14 error checking sdram width 08 08 00 00 08 08 15 not used 00 00 00 00 00 00 16 burst length supported 0c 0c 0c 0c 0c 0c 17 number of banks on sdram device 04 04 04 04 04 04 18 supported cas latencies 70 70 70 70 70 70 19 dimm mechanical characteristics 01 01 01 01 01 01
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 43 10202006-l0sm-feyt 20dimm type information 020202020202 21 dimm attributes 00 00 00 00 00 00 22 component attributes 07 07 07 07 07 07 23 t ck @ cl max -1 (byte 18) [ns] 25 25 25 25 25 25 24 t ac sdram @ cl max -1 [ns] 40 40 40 40 40 40 25 t ck @ cl max -2 (byte 18) [ns] 3d 3d 3d 3d 3d 3d 26 t ac sdram @ cl max -2 [ns] 50 50 50 50 50 50 27 t rp.min [ns] 32 32 32 32 32 32 28 t rrd.min [ns] 1e 1e 1e 1e 1e 1e 29 t rcd.min [ns] 32 32 32 32 32 32 30 t ras.min [ns] 2d 2d 2d 2d 2d 2d 31 module density per rank 80 80 80 80 80 80 32 t as.min and t cs.min [ns] 17 17 17 17 17 17 33 t ah.min and t ch.min [ns] 25 25 25 25 25 25 34 t ds.min [ns] 05 05 05 05 05 05 35 t dh.min [ns] 12 12 12 12 12 12 36 t wr.min [ns] 3c 3c 3c 3c 3c 3c 37 t wtr.min [ns] 1e 1e 1e 1e 1e 1e 38 t rtp.min [ns] 1e 1e 1e 1e 1e 1e 39 analysis characteristics 00 00 00 00 00 00 40 t rc and t rfc extension 303030303030 41 t rc.min [ns] 39 39 39 39 39 39 42 t rfc.min [ns] 69 69 69 69 69 69 product type hys72t64000eu?25f?b2 hys72t64900eu?25f?b2 hys64t128020eu?25f?b2 hys64t128920eu?25f?b2 hys72t128020eu?25f?b2 hys72t128920eu?25f?b2 organization 512mb 512mb 1 gbyte 1 gbyte 1 gbyte 1 gbyte u 72 u 72 u 64 u 64 u 72 u 72 1 rank ( u 8) 1 rank ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) label code pc2? 6400e? 555 pc2? 6400e? 555 pc2? 6400u? 555 pc2? 6400u? 555 pc2? 6400e? 555 pc2? 6400e? 555 jedec spd revision rev. 1.2 rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 44 10202006-l0sm-feyt 43 t ck.max [ns] 80 80 80 80 80 80 44 t dqsq.max [ns] 14 14 14 14 14 14 45 t qhs.max [ns] 1e 1e 1e 1e 1e 1e 46 pll relock time 00 00 00 00 00 00 47 t case.max delta / ' t 4r4w delta 505050505050 48psi(t-a) dram 7a7a7a7a7a7a 49 ' t 0 (dt0) 5f5f5f5f5f5f 50 ' t 2n (dt2n, udimm) or ' t 2q (dt2q, rdimm) 3b3b3b3b3b3b 51 ' t 2p (dt2p) 36 36 36 36 36 36 52 ' t 3n (dt3n) 2e 2e 2e 2e 2e 2e 53 ' t 3p.fast (dt3p fast) 5a5a5a5a5a5a 54 ' t 3p.slow (dt3p slow) 2a2a2a2a2a2a 55 ' t 4r (dt4r) / ' t 4r4w sign (dt4r4w) 5a 5a 5a 5a 5a 5a 56 ' t 5b (dt5b) 22 22 22 22 22 22 57 ' t 7 (dt7) 272727272727 58psi(ca) pll 000000000000 59psi(ca) reg 000000000000 60 ' t pll (dtpll) 000000000000 61 ' t reg (dtreg) / toggle rate 00 00 00 00 00 00 62 spd revision 12 12 12 12 12 12 63 checksum of bytes 0-62 49 49 38 38 4a 4a 64 manufacturer?s jedec id code (1) 7f 7f 7f 7f 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 7f 7f 7f 7f product type hys72t64000eu?25f?b2 hys72t64900eu?25f?b2 hys64t128020eu?25f?b2 hys64t128920eu?25f?b2 hys72t128020eu?25f?b2 hys72t128920eu?25f?b2 organization 512mb 512mb 1 gbyte 1 gbyte 1 gbyte 1 gbyte u 72 u 72 u 64 u 64 u 72 u 72 1 rank ( u 8) 1 rank ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) label code pc2? 6400e? 555 pc2? 6400e? 555 pc2? 6400u? 555 pc2? 6400u? 555 pc2? 6400e? 555 pc2? 6400e? 555 jedec spd revision rev. 1.2 rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 45 10202006-l0sm-feyt 66 manufacturer?s jedec id code (3) 7f 7f 7f 7f 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 7f 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 00 00 00 72 module manufacturer location xx xx xx xx xx xx 73 product type, char 1 37 37 36 36 37 37 74 product type, char 2 32 32 34 34 32 32 75 product type, char 3 54 54 54 54 54 54 76 product type, char 4 36 36 31 31 31 31 77 product type, char 5 34 34 32 32 32 32 78 product type, char 6 30 39 38 38 38 38 79 product type, char 7 30 30 30 39 30 39 80 product type, char 8 30 30 32 32 32 32 81 product type, char 9 45 45 30 30 30 30 82 product type, char 10 55 55 45 45 45 45 83 product type, char 11 32 32 55 55 55 55 84 product type, char 12 35 35 32 32 32 32 85 product type, char 13 46 46 35 35 35 35 86 product type, char 14 42 42 46 46 46 46 87 product type, char 15 32 32 42 42 42 42 88 product type, char 16 20 20 32 32 32 32 product type hys72t64000eu?25f?b2 hys72t64900eu?25f?b2 hys64t128020eu?25f?b2 hys64t128920eu?25f?b2 hys72t128020eu?25f?b2 hys72t128920eu?25f?b2 organization 512mb 512mb 1 gbyte 1 gbyte 1 gbyte 1 gbyte u 72 u 72 u 64 u 64 u 72 u 72 1 rank ( u 8) 1 rank ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) label code pc2? 6400e? 555 pc2? 6400e? 555 pc2? 6400u? 555 pc2? 6400u? 555 pc2? 6400e? 555 pc2? 6400e? 555 jedec spd revision rev. 1.2 rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 46 10202006-l0sm-feyt 89 product type, char 17 20 20 20 20 20 20 90 product type, char 18 20 20 20 20 20 20 91 module revision code 3x 0x 3x 0x 3x 0x 92 test program revisi on code xx xx xx xx xx xx 93 module manufacturing date year xx xx xx xx xx xx 94 module manufacturing date week xx xx xx xx xx xx 95 - 98 module serial number xx xx xx xx xx xx 99 - 127 not used 00 00 00 00 00 00 128 - 255 blank for customer use ff ff ff ff ff ff product type hys72t64000eu?25f?b2 hys72t64900eu?25f?b2 hys64t128020eu?25f?b2 hys64t128920eu?25f?b2 hys72t128020eu?25f?b2 hys72t128920eu?25f?b2 organization 512mb 512mb 1 gbyte 1 gbyte 1 gbyte 1 gbyte u 72 u 72 u 64 u 64 u 72 u 72 1 rank ( u 8) 1 rank ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) label code pc2? 6400e? 555 pc2? 6400e? 555 pc2? 6400u? 555 pc2? 6400u? 555 pc2? 6400e? 555 pc2? 6400e? 555 jedec spd revision rev. 1.2 rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 47 10202006-l0sm-feyt table 27 hys64t[32/64]x00eu-2.5-b2 product type hys64t32000eu?2.5?b2 hys64t32900eu?2.5?b2 hys64t64000eu?2.5?b2 hys64t64900eu?2.5?b2 organization 256mb 256mb 512mb 512mb u 64 u 64 u 64 u 64 1 rank ( u 16) 1 rank ( u 16) 1 rank ( u 8) 1 rank ( u 8) label code pc2? 6400u?666 pc2? 6400u?666 pc2? 6400u?666 pc2? 6400u?666 jedec spd revision rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex 0 programmed spd bytes in eeprom 80 80 80 80 1 total number of bytes in eeprom 08 08 08 08 2 memory type (ddr2) 08 08 08 08 3 number of row addresses 0d 0d 0e 0e 4 number of column addresses 0a 0a 0a 0a 5 dimm rank and stacking information 60 60 60 60 6 data width 40 40 40 40 7 not used 00 00 00 00 8 interface voltage level 05 05 05 05 9 t ck @ cl max (byte 18) [ns] 25 25 25 25 10 t ac sdram @ cl max (byte 18) [ns] 40 40 40 40 11 error correction support (non-ecc, ecc) 00 00 00 00 12 refresh rate and type 82 82 82 82 13 primary sdram width 10 10 08 08 14 error checking sdram width 00 00 00 00 15 not used 00 00 00 00 16 burst length supported 0c 0c 0c 0c 17 number of banks on sdram device 04 04 04 04 18 supported cas latencies 70 70 70 70 19 dimm mechanical characteristics 01 01 01 01 20 dimm type information 02 02 02 02 21 dimm attributes 00 00 00 00 22 component attributes 07 07 07 07
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 48 10202006-l0sm-feyt 23 t ck @ cl max -1 (byte 18) [ns] 30 30 30 30 24 t ac sdram @ cl max -1 [ns] 45 45 45 45 25 t ck @ cl max -2 (byte 18) [ns] 3d 3d 3d 3d 26 t ac sdram @ cl max -2 [ns] 50 50 50 50 27 t rp.min [ns] 3c 3c 3c 3c 28 t rrd.min [ns] 28 28 1e 1e 29 t rcd.min [ns] 3c 3c 3c 3c 30 t ras.min [ns] 2d 2d 2d 2d 31 module density per rank 40 40 80 80 32 t as.min and t cs.min [ns] 17 17 17 17 33 t ah.min and t ch.min [ns] 25 25 25 25 34 t ds.min [ns] 05 05 05 05 35 t dh.min [ns] 12 12 12 12 36 t wr.min [ns] 3c 3c 3c 3c 37 t wtr.min [ns] 1e 1e 1e 1e 38 t rtp.min [ns] 1e 1e 1e 1e 39 analysis characteristics 00 00 00 00 40 t rc and t rfc extension 00000000 41 t rc.min [ns] 3c 3c 3c 3c 42 t rfc.min [ns] 69 69 69 69 43 t ck.max [ns] 80 80 80 80 44 t dqsq.max [ns] 14 14 14 14 45 t qhs.max [ns] 1e 1e 1e 1e 46 pll relock time 00 00 00 00 47 t case.max delta / ' t 4r4w delta 56 56 50 50 48 psi(t-a) dram 7a 7a 7a 7a product type hys64t32000eu?2.5?b2 hys64t32900eu?2.5?b2 hys64t64000eu?2.5?b2 hys64t64900eu?2.5?b2 organization 256mb 256mb 512mb 512mb u 64 u 64 u 64 u 64 1 rank ( u 16) 1 rank ( u 16) 1 rank ( u 8) 1 rank ( u 8) label code pc2? 6400u?666 pc2? 6400u?666 pc2? 6400u?666 pc2? 6400u?666 jedec spd revision rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 49 10202006-l0sm-feyt 49 ' t 0 (dt0) 77 77 5b 5b 50 ' t 2n (dt2n, udimm) or ' t 2q (dt2q, rdimm) 3b 3b 3b 3b 51 ' t 2p (dt2p) 36 36 36 36 52 ' t 3n (dt3n) 2e 2e 2e 2e 53 ' t 3p.fast (dt3p fast) 5a5a5a5a 54 ' t 3p.slow (dt3p slow) 2a2a2a2a 55 ' t 4r (dt4r) / ' t 4r4w sign (dt4r4w) 68 68 5a 5a 56 ' t 5b (dt5b) 22 22 22 22 57 ' t 7 (dt7) 3b 3b 25 25 58 psi(ca) pll 00 00 00 00 59 psi(ca) reg 00 00 00 00 60 ' t pll (dtpll) 00000000 61 ' t reg (dtreg) / toggle rate 00 00 00 00 62 spd revision 12 12 12 12 63 checksum of bytes 0-62 3f 3f 28 28 64 manufacturer?s jedec id code (1) 7f 7f 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 7f 7f 66 manufacturer?s jedec id code (3) 7f 7f 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 00 72 module manufacturer location xx xx xx xx 73 product type, char 1 36 36 36 36 74 product type, char 2 34 34 34 34 product type hys64t32000eu?2.5?b2 hys64t32900eu?2.5?b2 hys64t64000eu?2.5?b2 hys64t64900eu?2.5?b2 organization 256mb 256mb 512mb 512mb u 64 u 64 u 64 u 64 1 rank ( u 16) 1 rank ( u 16) 1 rank ( u 8) 1 rank ( u 8) label code pc2? 6400u?666 pc2? 6400u?666 pc2? 6400u?666 pc2? 6400u?666 jedec spd revision rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 50 10202006-l0sm-feyt 75 product type, char 3 54 54 54 54 76 product type, char 4 33 33 36 36 77 product type, char 5 32 32 34 34 78 product type, char 6 30 39 30 39 79 product type, char 7 30 30 30 30 80 product type, char 8 30 30 30 30 81 product type, char 9 45 45 45 45 82 product type, char 10 55 55 55 55 83 product type, char 11 32 32 32 32 84 product type, char 12 2e 2e 2e 2e 85 product type, char 13 35 35 35 35 86 product type, char 14 42 42 42 42 87 product type, char 15 32 32 32 32 88 product type, char 16 20 20 20 20 89 product type, char 17 20 20 20 20 90 product type, char 18 20 20 20 20 91 module revision code 3x 0x 3x 0x 92 test program revision code xx xx xx xx 93 module manufacturing date year xx xx xx xx 94 module manufacturing date week xx xx xx xx 95 - 98 module serial number xx xx xx xx 99 - 127 not used 00 00 00 00 128 - 255 blank for customer use ff ff ff ff product type hys64t32000eu?2.5?b2 hys64t32900eu?2.5?b2 hys64t64000eu?2.5?b2 hys64t64900eu?2.5?b2 organization 256mb 256mb 512mb 512mb u 64 u 64 u 64 u 64 1 rank ( u 16) 1 rank ( u 16) 1 rank ( u 8) 1 rank ( u 8) label code pc2? 6400u?666 pc2? 6400u?666 pc2? 6400u?666 pc2? 6400u?666 jedec spd revision rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 51 10202006-l0sm-feyt table 28 hys[64/72]t[64/128]xx0eu-2.5-b2 product type hys72t64000eu?2.5?b2 hys72t64900eu?2.5?b2 hys64t128020eu?2.5?b2 hys64t128920eu?2.5?b2 hys72t128020eu?2.5?b2 hys72t128920eu?2.5?b2 organization 512mb 512mb 1 gbyte 1 gbyte 1 gbyte 1 gbyte u 72 u 72 u 64 u 64 u 72 u 72 1 rank ( u 8) 1 rank ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) label code pc2? 6400e? 666 pc2? 6400e? 666 pc2? 6400u? 666 pc2? 6400u? 666 pc2? 6400e? 666 pc2? 6400e? 666 jedec spd revision rev. 1.2 rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hex hex 0 programmed spd bytes in eeprom 80 80 80 80 80 80 1 total number of bytes in eeprom 08 08 08 08 08 08 2 memory type (ddr2) 08 08 08 08 08 08 3 number of row addresses 0e 0e 0e 0e 0e 0e 4 number of column addresses 0a 0a 0a 0a 0a 0a 5 dimm rank and stacking information 60 60 61 61 61 61 6 data width 484840404848 7 not used 00 00 00 00 00 00 8 interface voltage level 05 05 05 05 05 05 9 t ck @ cl max (byte 18) [ns] 25 25 25 25 25 25 10 t ac sdram @ cl max (byte 18) [ns] 40 40 40 40 40 40 11 error correction support (non-ecc, ecc) 02 02 00 00 02 02 12 refresh rate and type 82 82 82 82 82 82 13 primary sdram width 08 08 08 08 08 08 14 error checking sdram width 08 08 00 00 08 08 15 not used 00 00 00 00 00 00 16 burst length supported 0c 0c 0c 0c 0c 0c 17 number of banks on sdram device 04 04 04 04 04 04 18 supported cas latencies 70 70 70 70 70 70 19 dimm mechanical characteristics 01 01 01 01 01 01
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 52 10202006-l0sm-feyt 20dimm type information 020202020202 21 dimm attributes 00 00 00 00 00 00 22 component attributes 07 07 07 07 07 07 23 t ck @ cl max -1 (byte 18) [ns] 30 30 30 30 30 30 24 t ac sdram @ cl max -1 [ns] 45 45 45 45 45 45 25 t ck @ cl max -2 (byte 18) [ns] 3d 3d 3d 3d 3d 3d 26 t ac sdram @ cl max -2 [ns] 50 50 50 50 50 50 27 t rp.min [ns] 3c 3c 3c 3c 3c 3c 28 t rrd.min [ns] 1e 1e 1e 1e 1e 1e 29 t rcd.min [ns] 3c 3c 3c 3c 3c 3c 30 t ras.min [ns] 2d 2d 2d 2d 2d 2d 31 module density per rank 80 80 80 80 80 80 32 t as.min and t cs.min [ns] 17 17 17 17 17 17 33 t ah.min and t ch.min [ns] 25 25 25 25 25 25 34 t ds.min [ns] 05 05 05 05 05 05 35 t dh.min [ns] 12 12 12 12 12 12 36 t wr.min [ns] 3c 3c 3c 3c 3c 3c 37 t wtr.min [ns] 1e 1e 1e 1e 1e 1e 38 t rtp.min [ns] 1e 1e 1e 1e 1e 1e 39 analysis characteristics 00 00 00 00 00 00 40 t rc and t rfc extension 000000000000 41 t rc.min [ns] 3c 3c 3c 3c 3c 3c 42 t rfc.min [ns] 69 69 69 69 69 69 product type hys72t64000eu?2.5?b2 hys72t64900eu?2.5?b2 hys64t128020eu?2.5?b2 hys64t128920eu?2.5?b2 hys72t128020eu?2.5?b2 hys72t128920eu?2.5?b2 organization 512mb 512mb 1 gbyte 1 gbyte 1 gbyte 1 gbyte u 72 u 72 u 64 u 64 u 72 u 72 1 rank ( u 8) 1 rank ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) label code pc2? 6400e? 666 pc2? 6400e? 666 pc2? 6400u? 666 pc2? 6400u? 666 pc2? 6400e? 666 pc2? 6400e? 666 jedec spd revision rev. 1.2 rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 53 10202006-l0sm-feyt 43 t ck.max [ns] 80 80 80 80 80 80 44 t dqsq.max [ns] 14 14 14 14 14 14 45 t qhs.max [ns] 1e 1e 1e 1e 1e 1e 46 pll relock time 00 00 00 00 00 00 47 t case.max delta / ' t 4r4w delta 505050505050 48psi(t-a) dram 7a7a7a7a7a7a 49 ' t 0 (dt0) 5b5b5b5b5b5b 50 ' t 2n (dt2n, udimm) or ' t 2q (dt2q, rdimm) 3b3b3b3b3b3b 51 ' t 2p (dt2p) 36 36 36 36 36 36 52 ' t 3n (dt3n) 2e 2e 2e 2e 2e 2e 53 ' t 3p.fast (dt3p fast) 5a5a5a5a5a5a 54 ' t 3p.slow (dt3p slow) 2a2a2a2a2a2a 55 ' t 4r (dt4r) / ' t 4r4w sign (dt4r4w) 5a 5a 5a 5a 5a 5a 56 ' t 5b (dt5b) 22 22 22 22 22 22 57 ' t 7 (dt7) 252525252525 58psi(ca) pll 000000000000 59psi(ca) reg 000000000000 60 ' t pll (dtpll) 000000000000 61 ' t reg (dtreg) / toggle rate 00 00 00 00 00 00 62 spd revision 12 12 12 12 12 12 63 checksum of bytes 0-62 3a 3a 29 29 3b 3b 64 manufacturer?s jedec id code (1) 7f 7f 7f 7f 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 7f 7f 7f 7f product type hys72t64000eu?2.5?b2 hys72t64900eu?2.5?b2 hys64t128020eu?2.5?b2 hys64t128920eu?2.5?b2 hys72t128020eu?2.5?b2 hys72t128920eu?2.5?b2 organization 512mb 512mb 1 gbyte 1 gbyte 1 gbyte 1 gbyte u 72 u 72 u 64 u 64 u 72 u 72 1 rank ( u 8) 1 rank ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) label code pc2? 6400e? 666 pc2? 6400e? 666 pc2? 6400u? 666 pc2? 6400u? 666 pc2? 6400e? 666 pc2? 6400e? 666 jedec spd revision rev. 1.2 rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 54 10202006-l0sm-feyt 66 manufacturer?s jedec id code (3) 7f 7f 7f 7f 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 7f 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 00 00 00 72 module manufacturer location xx xx xx xx xx xx 73 product type, char 1 37 37 36 36 37 37 74 product type, char 2 32 32 34 34 32 32 75 product type, char 3 54 54 54 54 54 54 76 product type, char 4 36 36 31 31 31 31 77 product type, char 5 34 34 32 32 32 32 78 product type, char 6 30 39 38 38 38 38 79 product type, char 7 30 30 30 39 30 39 80 product type, char 8 30 30 32 32 32 32 81 product type, char 9 45 45 30 30 30 30 82 product type, char 10 55 55 45 45 45 45 83 product type, char 11 32 32 55 55 55 55 84 product type, char 12 2e 2e 32 32 32 32 85 product type, char 13 35 35 2e 2e 2e 2e 86 product type, char 14 42 42 35 35 35 35 87 product type, char 15 32 32 42 42 42 42 88 product type, char 16 20 20 32 32 32 32 product type hys72t64000eu?2.5?b2 hys72t64900eu?2.5?b2 hys64t128020eu?2.5?b2 hys64t128920eu?2.5?b2 hys72t128020eu?2.5?b2 hys72t128920eu?2.5?b2 organization 512mb 512mb 1 gbyte 1 gbyte 1 gbyte 1 gbyte u 72 u 72 u 64 u 64 u 72 u 72 1 rank ( u 8) 1 rank ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) label code pc2? 6400e? 666 pc2? 6400e? 666 pc2? 6400u? 666 pc2? 6400u? 666 pc2? 6400e? 666 pc2? 6400e? 666 jedec spd revision rev. 1.2 rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 55 10202006-l0sm-feyt 89 product type, char 17 20 20 20 20 20 20 90 product type, char 18 20 20 20 20 20 20 91 module revision code 3x 0x 3x 0x 3x 0x 92 test program revisi on code xx xx xx xx xx xx 93 module manufacturing date year xx xx xx xx xx xx 94 module manufacturing date week xx xx xx xx xx xx 95 - 98 module serial number xx xx xx xx xx xx 99 - 127 not used 00 00 00 00 00 00 128 - 255 blank for customer use ff ff ff ff ff ff product type hys72t64000eu?2.5?b2 hys72t64900eu?2.5?b2 hys64t128020eu?2.5?b2 hys64t128920eu?2.5?b2 hys72t128020eu?2.5?b2 hys72t128920eu?2.5?b2 organization 512mb 512mb 1 gbyte 1 gbyte 1 gbyte 1 gbyte u 72 u 72 u 64 u 64 u 72 u 72 1 rank ( u 8) 1 rank ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) label code pc2? 6400e? 666 pc2? 6400e? 666 pc2? 6400u? 666 pc2? 6400u? 666 pc2? 6400e? 666 pc2? 6400e? 666 jedec spd revision rev. 1.2 rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 56 10202006-l0sm-feyt table 29 hys64t[32/64]x00eu-3-b2 product type hys64t32000eu?3?b2 hys64t32900eu?3?b2 hys64t64000eu?3?b2 hys64t64900eu?3?b2 organization 256mb 256mb 512mb 512mb u 64 u 64 u 64 u 64 1 rank ( u 16) 1 rank ( u 16) 1 rank ( u 8) 1 rank ( u 8) label code pc2? 5300u?444 pc2? 5300u?444 pc2? 5300u?444 pc2? 5300u?444 jedec spd revision rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex 0 programmed spd bytes in eeprom 80 80 80 80 1 total number of bytes in eeprom 08 08 08 08 2 memory type (ddr2) 08 08 08 08 3 number of row addresses 0d 0d 0e 0e 4 number of column addresses 0a 0a 0a 0a 5 dimm rank and stacking information 60 60 60 60 6 data width 40 40 40 40 7 not used 00 00 00 00 8 interface voltage level 05 05 05 05 9 t ck @ cl max (byte 18) [ns] 30 30 30 30 10 t ac sdram @ cl max (byte 18) [ns] 45 45 45 45 11 error correction support (non-ecc, ecc) 00 00 00 00 12 refresh rate and type 82 82 82 82 13 primary sdram width 10 10 08 08 14 error checking sdram width 00 00 00 00 15 not used 00 00 00 00 16 burst length supported 0c 0c 0c 0c 17 number of banks on sdram device 04 04 04 04 18 supported cas latencies 38 38 38 38 19 dimm mechanical characteristics 01 01 01 01 20 dimm type information 02 02 02 02 21 dimm attributes 00 00 00 00 22 component attributes 07 07 07 07
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 57 10202006-l0sm-feyt 23 t ck @ cl max -1 (byte 18) [ns] 30 30 30 30 24 t ac sdram @ cl max -1 [ns] 45 45 45 45 25 t ck @ cl max -2 (byte 18) [ns] 50 50 50 50 26 t ac sdram @ cl max -2 [ns] 60 60 60 60 27 t rp.min [ns] 30 30 30 30 28 t rrd.min [ns] 28 28 1e 1e 29 t rcd.min [ns] 30 30 30 30 30 t ras.min [ns] 2d 2d 2d 2d 31 module density per rank 40 40 80 80 32 t as.min and t cs.min [ns] 20 20 20 20 33 t ah.min and t ch.min [ns] 27 27 27 27 34 t ds.min [ns] 10 10 10 10 35 t dh.min [ns] 17 17 17 17 36 t wr.min [ns] 3c 3c 3c 3c 37 t wtr.min [ns] 1e 1e 1e 1e 38 t rtp.min [ns] 1e 1e 1e 1e 39 analysis characteristics 00 00 00 00 40 t rc and t rfc extension 00000000 41 t rc.min [ns] 39 39 39 39 42 t rfc.min [ns] 69 69 69 69 43 t ck.max [ns] 80 80 80 80 44 t dqsq.max [ns] 18 18 18 18 45 t qhs.max [ns] 22 22 22 22 46 pll relock time 00 00 00 00 47 t case.max delta / ' t 4r4w delta 54 54 50 50 48 psi(t-a) dram 7a 7a 7a 7a product type hys64t32000eu?3?b2 hys64t32900eu?3?b2 hys64t64000eu?3?b2 hys64t64900eu?3?b2 organization 256mb 256mb 512mb 512mb u 64 u 64 u 64 u 64 1 rank ( u 16) 1 rank ( u 16) 1 rank ( u 8) 1 rank ( u 8) label code pc2? 5300u?444 pc2? 5300u?444 pc2? 5300u?444 pc2? 5300u?444 jedec spd revision rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 58 10202006-l0sm-feyt 49 ' t 0 (dt0) 6f 6f 53 53 50 ' t 2n (dt2n, udimm) or ' t 2q (dt2q, rdimm) 34 34 34 34 51 ' t 2p (dt2p) 36 36 36 36 52 ' t 3n (dt3n) 27 27 27 27 53 ' t 3p.fast (dt3p fast) 4c4c4c4c 54 ' t 3p.slow (dt3p slow) 2a2a2a2a 55 ' t 4r (dt4r) / ' t 4r4w sign (dt4r4w) 5a 5a 4c 4c 56 ' t 5b (dt5b) 20 20 20 20 57 ' t 7 (dt7) 3a 3a 25 25 58 psi(ca) pll 00 00 00 00 59 psi(ca) reg 00 00 00 00 60 ' t pll (dtpll) 00000000 61 ' t reg (dtreg) / toggle rate 00 00 00 00 62 spd revision 12 12 12 12 63 checksum of bytes 0-62 0b 0b f7 f7 64 manufacturer?s jedec id code (1) 7f 7f 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 7f 7f 66 manufacturer?s jedec id code (3) 7f 7f 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 00 72 module manufacturer location xx xx xx xx 73 product type, char 1 36 36 36 36 74 product type, char 2 34 34 34 34 product type hys64t32000eu?3?b2 hys64t32900eu?3?b2 hys64t64000eu?3?b2 hys64t64900eu?3?b2 organization 256mb 256mb 512mb 512mb u 64 u 64 u 64 u 64 1 rank ( u 16) 1 rank ( u 16) 1 rank ( u 8) 1 rank ( u 8) label code pc2? 5300u?444 pc2? 5300u?444 pc2? 5300u?444 pc2? 5300u?444 jedec spd revision rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 59 10202006-l0sm-feyt 75 product type, char 3 54 54 54 54 76 product type, char 4 33 33 36 36 77 product type, char 5 32 32 34 34 78 product type, char 6 30 39 30 39 79 product type, char 7 30 30 30 30 80 product type, char 8 30 30 30 30 81 product type, char 9 45 45 45 45 82 product type, char 10 55 55 55 55 83 product type, char 11 33 33 33 33 84 product type, char 12 42 42 42 42 85 product type, char 13 32 32 32 32 86 product type, char 14 20 20 20 20 87 product type, char 15 20 20 20 20 88 product type, char 16 20 20 20 20 89 product type, char 17 20 20 20 20 90 product type, char 18 20 20 20 20 91 module revision code 2x 0x 2x 0x 92 test program revision code xx xx xx xx 93 module manufacturing date year xx xx xx xx 94 module manufacturing date week xx xx xx xx 95 - 98 module serial number xx xx xx xx 99 - 127 not used 00 00 00 00 128 - 255 blank for customer use ff ff ff ff product type hys64t32000eu?3?b2 hys64t32900eu?3?b2 hys64t64000eu?3?b2 hys64t64900eu?3?b2 organization 256mb 256mb 512mb 512mb u 64 u 64 u 64 u 64 1 rank ( u 16) 1 rank ( u 16) 1 rank ( u 8) 1 rank ( u 8) label code pc2? 5300u?444 pc2? 5300u?444 pc2? 5300u?444 pc2? 5300u?444 jedec spd revision rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 60 10202006-l0sm-feyt table 30 hys[64/72]t[64/128]xx0eu-3-b2 product type hys72t64000eu?3?b2 hys72t64900eu?3?b2 hys64t128020eu?3?b2 hys64t128920eu?3?b2 hys72t128020eu?3?b2 hys72t128920eu?3?b2 organization 512mb 512mb 1 gbyte 1 gbyte 1 gbyte 1 gbyte u 72 u 72 u 64 u 64 u 72 u 72 1 rank ( u 8) 1 rank ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) label code pc2? 5300e? 444 pc2? 5300e? 444 pc2? 5300u? 444 pc2? 5300u? 444 pc2? 5300e? 444 pc2? 5300e? 444 jedec spd revision rev. 1.2 rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hex hex 0 programmed spd bytes in eeprom 80 80 80 80 80 80 1 total number of bytes in eeprom 08 08 08 08 08 08 2 memory type (ddr2) 08 08 08 08 08 08 3 number of row addresses 0e 0e 0e 0e 0e 0e 4 number of column addresses 0a 0a 0a 0a 0a 0a 5 dimm rank and stacking information 60 60 61 61 61 61 6 data width 484840404848 7 not used 00 00 00 00 00 00 8 interface voltage level 05 05 05 05 05 05 9 t ck @ cl max (byte 18) [ns] 30 30 30 30 30 30 10 t ac sdram @ cl max (byte 18) [ns] 45 45 45 45 45 45 11 error correction support (non-ecc, ecc) 02 02 00 00 02 02 12 refresh rate and type 82 82 82 82 82 82 13 primary sdram width 08 08 08 08 08 08 14 error checking sdram width 08 08 00 00 08 08 15 not used 00 00 00 00 00 00 16 burst length supported 0c 0c 0c 0c 0c 0c 17 number of banks on sdram device 04 04 04 04 04 04 18 supported cas latencies 38 38 38 38 38 38 19 dimm mechanical characteristics 01 01 01 01 01 01 20dimm type information 020202020202
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 61 10202006-l0sm-feyt 21 dimm attributes 00 00 00 00 00 00 22 component attributes 07 07 07 07 07 07 23 t ck @ cl max -1 (byte 18) [ns] 30 30 30 30 30 30 24 t ac sdram @ cl max -1 [ns] 45 45 45 45 45 45 25 t ck @ cl max -2 (byte 18) [ns] 50 50 50 50 50 50 26 t ac sdram @ cl max -2 [ns] 60 60 60 60 60 60 27 t rp.min [ns] 30 30 30 30 30 30 28 t rrd.min [ns] 1e 1e 1e 1e 1e 1e 29 t rcd.min [ns] 30 30 30 30 30 30 30 t ras.min [ns] 2d 2d 2d 2d 2d 2d 31 module density per rank 80 80 80 80 80 80 32 t as.min and t cs.min [ns] 20 20 20 20 20 20 33 t ah.min and t ch.min [ns] 27 27 27 27 27 27 34 t ds.min [ns] 10 10 10 10 10 10 35 t dh.min [ns] 17 17 17 17 17 17 36 t wr.min [ns] 3c 3c 3c 3c 3c 3c 37 t wtr.min [ns] 1e 1e 1e 1e 1e 1e 38 t rtp.min [ns] 1e 1e 1e 1e 1e 1e 39 analysis characteristics 00 00 00 00 00 00 40 t rc and t rfc extension 000000000000 41 t rc.min [ns] 39 39 39 39 39 39 42 t rfc.min [ns] 69 69 69 69 69 69 43 t ck.max [ns] 80 80 80 80 80 80 product type hys72t64000eu?3?b2 hys72t64900eu?3?b2 hys64t128020eu?3?b2 hys64t128920eu?3?b2 hys72t128020eu?3?b2 hys72t128920eu?3?b2 organization 512mb 512mb 1 gbyte 1 gbyte 1 gbyte 1 gbyte u 72 u 72 u 64 u 64 u 72 u 72 1 rank ( u 8) 1 rank ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) label code pc2? 5300e? 444 pc2? 5300e? 444 pc2? 5300u? 444 pc2? 5300u? 444 pc2? 5300e? 444 pc2? 5300e? 444 jedec spd revision rev. 1.2 rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 62 10202006-l0sm-feyt 44 t dqsq.max [ns] 18 18 18 18 18 18 45 t qhs.max [ns] 22 22 22 22 22 22 46 pll relock time 00 00 00 00 00 00 47 t case.max delta / ' t 4r4w delta 505050505050 48psi(t-a) dram 7a7a7a7a7a7a 49 ' t 0 (dt0) 535353535353 50 ' t 2n (dt2n, udimm) or ' t 2q (dt2q, rdimm) 343434343434 51 ' t 2p (dt2p) 36 36 36 36 36 36 52 ' t 3n (dt3n) 27 27 27 27 27 27 53 ' t 3p.fast (dt3p fast) 4c4c4c4c4c4c 54 ' t 3p.slow (dt3p slow) 2a2a2a2a2a2a 55 ' t 4r (dt4r) / ' t 4r4w sign (dt4r4w) 4c 4c 4c 4c 4c 4c 56 ' t 5b (dt5b) 20 20 20 20 20 20 57 ' t 7 (dt7) 252525252525 58psi(ca) pll 000000000000 59psi(ca) reg 000000000000 60 ' t pll (dtpll) 000000000000 61 ' t reg (dtreg) / toggle rate 00 00 00 00 00 00 62 spd revision 12 12 12 12 12 12 63 checksum of bytes 0-62 09 09 f8 f8 0a 0a 64 manufacturer?s jedec id code (1) 7f 7f 7f 7f 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 7f 7f 7f 7f 66 manufacturer?s jedec id code (3) 7f 7f 7f 7f 7f 7f product type hys72t64000eu?3?b2 hys72t64900eu?3?b2 hys64t128020eu?3?b2 hys64t128920eu?3?b2 hys72t128020eu?3?b2 hys72t128920eu?3?b2 organization 512mb 512mb 1 gbyte 1 gbyte 1 gbyte 1 gbyte u 72 u 72 u 64 u 64 u 72 u 72 1 rank ( u 8) 1 rank ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) label code pc2? 5300e? 444 pc2? 5300e? 444 pc2? 5300u? 444 pc2? 5300u? 444 pc2? 5300e? 444 pc2? 5300e? 444 jedec spd revision rev. 1.2 rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 63 10202006-l0sm-feyt 67 manufacturer?s jedec id code (4) 7f 7f 7f 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 00 00 00 72 module manufacturer location xx xx xx xx xx xx 73 product type, char 1 37 37 36 36 37 37 74 product type, char 2 32 32 34 34 32 32 75 product type, char 3 54 54 54 54 54 54 76 product type, char 4 36 36 31 31 31 31 77 product type, char 5 34 34 32 32 32 32 78 product type, char 6 30 39 38 38 38 38 79 product type, char 7 30 30 30 39 30 39 80 product type, char 8 30 30 32 32 32 32 81 product type, char 9 45 45 30 30 30 30 82 product type, char 10 55 55 45 45 45 45 83 product type, char 11 33 33 55 55 55 55 84 product type, char 12 42 42 33 33 33 33 85 product type, char 13 32 32 42 42 42 42 86 product type, char 14 20 20 32 32 32 32 87 product type, char 15 20 20 20 20 20 20 88 product type, char 16 20 20 20 20 20 20 89 product type, char 17 20 20 20 20 20 20 product type hys72t64000eu?3?b2 hys72t64900eu?3?b2 hys64t128020eu?3?b2 hys64t128920eu?3?b2 hys72t128020eu?3?b2 hys72t128920eu?3?b2 organization 512mb 512mb 1 gbyte 1 gbyte 1 gbyte 1 gbyte u 72 u 72 u 64 u 64 u 72 u 72 1 rank ( u 8) 1 rank ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) label code pc2? 5300e? 444 pc2? 5300e? 444 pc2? 5300u? 444 pc2? 5300u? 444 pc2? 5300e? 444 pc2? 5300e? 444 jedec spd revision rev. 1.2 rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 64 10202006-l0sm-feyt 90 product type, char 18 20 20 20 20 20 20 91 module revision code 2x 0x 2x 0x 2x 0x 92 test program revisi on code xx xx xx xx xx xx 93 module manufacturing date year xx xx xx xx xx xx 94 module manufacturing date week xx xx xx xx xx xx 95 - 98 module serial number xx xx xx xx xx xx 99 - 127 not used 00 00 00 00 00 00 128 - 255 blank for customer use ff ff ff ff ff ff product type hys72t64000eu?3?b2 hys72t64900eu?3?b2 hys64t128020eu?3?b2 hys64t128920eu?3?b2 hys72t128020eu?3?b2 hys72t128920eu?3?b2 organization 512mb 512mb 1 gbyte 1 gbyte 1 gbyte 1 gbyte u 72 u 72 u 64 u 64 u 72 u 72 1 rank ( u 8) 1 rank ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) label code pc2? 5300e? 444 pc2? 5300e? 444 pc2? 5300u? 444 pc2? 5300u? 444 pc2? 5300e? 444 pc2? 5300e? 444 jedec spd revision rev. 1.2 rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 65 10202006-l0sm-feyt table 31 hys64t[32/64]x00eu-3s-b2 product type hys64t32000eu?3s?b2 hys64t32900eu?3s?b2 hys64t64000eu?3s?b2 hys64t64900eu?3s?b2 organization 256mb 256mb 512mb 512mb u 64 u 64 u 64 u 64 1 rank ( u 16) 1 rank ( u 16) 1 rank ( u 8) 1 rank ( u 8) label code pc2? 5300u?555 pc2? 5300u?555 pc2? 5300u?555 pc2? 5300u?555 jedec spd revision rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex 0 programmed spd bytes in eeprom 80 80 80 80 1 total number of bytes in eeprom 08 08 08 08 2 memory type (ddr2) 08 08 08 08 3 number of row addresses 0d 0d 0e 0e 4 number of column addresses 0a 0a 0a 0a 5 dimm rank and stacking information 60 60 60 60 6 data width 40 40 40 40 7 not used 00 00 00 00 8 interface voltage level 05 05 05 05 9 t ck @ cl max (byte 18) [ns] 30 30 30 30 10 t ac sdram @ cl max (byte 18) [ns] 45 45 45 45 11 error correction support (non-ecc, ecc) 00 00 00 00 12 refresh rate and type 82 82 82 82 13 primary sdram width 10 10 08 08 14 error checking sdram width 00 00 00 00 15 not used 00 00 00 00 16 burst length supported 0c 0c 0c 0c 17 number of banks on sdram device 04 04 04 04 18 supported cas latencies 38 38 38 38 19 dimm mechanical characteristics 01 01 01 01 20 dimm type information 02 02 02 02 21 dimm attributes 00 00 00 00 22 component attributes 07 07 07 07
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 66 10202006-l0sm-feyt 23 t ck @ cl max -1 (byte 18) [ns] 3d 3d 3d 3d 24 t ac sdram @ cl max -1 [ns] 50 50 50 50 25 t ck @ cl max -2 (byte 18) [ns] 50 50 50 50 26 t ac sdram @ cl max -2 [ns] 60 60 60 60 27 t rp.min [ns] 3c 3c 3c 3c 28 t rrd.min [ns] 28 28 1e 1e 29 t rcd.min [ns] 3c 3c 3c 3c 30 t ras.min [ns] 2d 2d 2d 2d 31 module density per rank 40 40 80 80 32 t as.min and t cs.min [ns] 20 20 20 20 33 t ah.min and t ch.min [ns] 27 27 27 27 34 t ds.min [ns] 10 10 10 10 35 t dh.min [ns] 17 17 17 17 36 t wr.min [ns] 3c 3c 3c 3c 37 t wtr.min [ns] 1e 1e 1e 1e 38 t rtp.min [ns] 1e 1e 1e 1e 39 analysis characteristics 00 00 00 00 40 t rc and t rfc extension 00000000 41 t rc.min [ns] 3c 3c 3c 3c 42 t rfc.min [ns] 69 69 69 69 43 t ck.max [ns] 80 80 80 80 44 t dqsq.max [ns] 18 18 18 18 45 t qhs.max [ns] 22 22 22 22 46 pll relock time 00 00 00 00 47 t case.max delta / ' t 4r4w delta 54 54 50 50 48 psi(t-a) dram 7a 7a 7a 7a product type hys64t32000eu?3s?b2 hys64t32900eu?3s?b2 hys64t64000eu?3s?b2 hys64t64900eu?3s?b2 organization 256mb 256mb 512mb 512mb u 64 u 64 u 64 u 64 1 rank ( u 16) 1 rank ( u 16) 1 rank ( u 8) 1 rank ( u 8) label code pc2? 5300u?555 pc2? 5300u?555 pc2? 5300u?555 pc2? 5300u?555 jedec spd revision rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 67 10202006-l0sm-feyt 49 ' t 0 (dt0) 67 67 4b 4b 50 ' t 2n (dt2n, udimm) or ' t 2q (dt2q, rdimm) 34 34 34 34 51 ' t 2p (dt2p) 36 36 36 36 52 ' t 3n (dt3n) 27 27 27 27 53 ' t 3p.fast (dt3p fast) 4c4c4c4c 54 ' t 3p.slow (dt3p slow) 2a2a2a2a 55 ' t 4r (dt4r) / ' t 4r4w sign (dt4r4w) 5a 5a 4c 4c 56 ' t 5b (dt5b) 20 20 20 20 57 ' t 7 (dt7) 38382323 58 psi(ca) pll 00 00 00 00 59 psi(ca) reg 00 00 00 00 60 ' t pll (dtpll) 00000000 61 ' t reg (dtreg) / toggle rate 00 00 00 00 62 spd revision 12 12 12 12 63 checksum of bytes 0-62 34 34 20 20 64 manufacturer?s jedec id code (1) 7f 7f 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 7f 7f 66 manufacturer?s jedec id code (3) 7f 7f 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 00 72 module manufacturer location xx xx xx xx 73 product type, char 1 36 36 36 36 74 product type, char 2 34 34 34 34 product type hys64t32000eu?3s?b2 hys64t32900eu?3s?b2 hys64t64000eu?3s?b2 hys64t64900eu?3s?b2 organization 256mb 256mb 512mb 512mb u 64 u 64 u 64 u 64 1 rank ( u 16) 1 rank ( u 16) 1 rank ( u 8) 1 rank ( u 8) label code pc2? 5300u?555 pc2? 5300u?555 pc2? 5300u?555 pc2? 5300u?555 jedec spd revision rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 68 10202006-l0sm-feyt 75 product type, char 3 54 54 54 54 76 product type, char 4 33 33 36 36 77 product type, char 5 32 32 34 34 78 product type, char 6 30 39 30 39 79 product type, char 7 30 30 30 30 80 product type, char 8 30 30 30 30 81 product type, char 9 45 45 45 45 82 product type, char 10 55 55 55 55 83 product type, char 11 33 33 33 33 84 product type, char 12 53 53 53 53 85 product type, char 13 42 42 42 42 86 product type, char 14 32 32 32 32 87 product type, char 15 20 20 20 20 88 product type, char 16 20 20 20 20 89 product type, char 17 20 20 20 20 90 product type, char 18 20 20 20 20 91 module revision code 2x 0x 2x 0x 92 test program revision code xx xx xx xx 93 module manufacturing date year xx xx xx xx 94 module manufacturing date week xx xx xx xx 95 - 98 module serial number xx xx xx xx 99 - 127 not used 00 00 00 00 128 - 255 blank for customer use ff ff ff ff product type hys64t32000eu?3s?b2 hys64t32900eu?3s?b2 hys64t64000eu?3s?b2 hys64t64900eu?3s?b2 organization 256mb 256mb 512mb 512mb u 64 u 64 u 64 u 64 1 rank ( u 16) 1 rank ( u 16) 1 rank ( u 8) 1 rank ( u 8) label code pc2? 5300u?555 pc2? 5300u?555 pc2? 5300u?555 pc2? 5300u?555 jedec spd revision rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 69 10202006-l0sm-feyt table 32 hys[64/72]t[64/128]xx0eu-3s-b2 product type hys72t64000eu?3s?b2 hys72t64900eu?3s?b2 hys64t128020eu?3s?b2 hys64t128920eu?3s?b2 hys72t128020eu?3s?b2 hys72t128920eu?3s?b2 organization 512mb 512mb 1 gbyte 1 gbyte 1 gbyte 1 gbyte u 72 u 72 u 64 u 64 u 72 u 72 1 rank ( u 8) 1 rank ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) label code pc2? 5300e? 555 pc2? 5300e? 555 pc2? 5300u? 555 pc2? 5300u? 555 pc2? 5300e? 555 pc2? 5300e? 555 jedec spd revision rev. 1.2 rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hex hex 0 programmed spd bytes in eeprom 80 80 80 80 80 80 1 total number of bytes in eeprom 08 08 08 08 08 08 2 memory type (ddr2) 08 08 08 08 08 08 3 number of row addresses 0e 0e 0e 0e 0e 0e 4 number of column addresses 0a 0a 0a 0a 0a 0a 5 dimm rank and stacking information 60 60 61 61 61 61 6 data width 484840404848 7 not used 00 00 00 00 00 00 8 interface voltage level 05 05 05 05 05 05 9 t ck @ cl max (byte 18) [ns] 30 30 30 30 30 30 10 t ac sdram @ cl max (byte 18) [ns] 45 45 45 45 45 45 11 error correction support (non-ecc, ecc) 02 02 00 00 02 02 12 refresh rate and type 82 82 82 82 82 82 13 primary sdram width 08 08 08 08 08 08 14 error checking sdram width 08 08 00 00 08 08 15 not used 00 00 00 00 00 00 16 burst length supported 0c 0c 0c 0c 0c 0c 17 number of banks on sdram device 04 04 04 04 04 04 18 supported cas latencies 38 38 38 38 38 38 19 dimm mechanical characteristics 01 01 01 01 01 01
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 70 10202006-l0sm-feyt 20dimm type information 020202020202 21 dimm attributes 00 00 00 00 00 00 22 component attributes 07 07 07 07 07 07 23 t ck @ cl max -1 (byte 18) [ns] 3d 3d 3d 3d 3d 3d 24 t ac sdram @ cl max -1 [ns] 50 50 50 50 50 50 25 t ck @ cl max -2 (byte 18) [ns] 50 50 50 50 50 50 26 t ac sdram @ cl max -2 [ns] 60 60 60 60 60 60 27 t rp.min [ns] 3c 3c 3c 3c 3c 3c 28 t rrd.min [ns] 1e 1e 1e 1e 1e 1e 29 t rcd.min [ns] 3c 3c 3c 3c 3c 3c 30 t ras.min [ns] 2d 2d 2d 2d 2d 2d 31 module density per rank 80 80 80 80 80 80 32 t as.min and t cs.min [ns] 20 20 20 20 20 20 33 t ah.min and t ch.min [ns] 27 27 27 27 27 27 34 t ds.min [ns] 10 10 10 10 10 10 35 t dh.min [ns] 17 17 17 17 17 17 36 t wr.min [ns] 3c 3c 3c 3c 3c 3c 37 t wtr.min [ns] 1e 1e 1e 1e 1e 1e 38 t rtp.min [ns] 1e 1e 1e 1e 1e 1e 39 analysis characteristics 00 00 00 00 00 00 40 t rc and t rfc extension 000000000000 41 t rc.min [ns] 3c 3c 3c 3c 3c 3c 42 t rfc.min [ns] 69 69 69 69 69 69 product type hys72t64000eu?3s?b2 hys72t64900eu?3s?b2 hys64t128020eu?3s?b2 hys64t128920eu?3s?b2 hys72t128020eu?3s?b2 hys72t128920eu?3s?b2 organization 512mb 512mb 1 gbyte 1 gbyte 1 gbyte 1 gbyte u 72 u 72 u 64 u 64 u 72 u 72 1 rank ( u 8) 1 rank ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) label code pc2? 5300e? 555 pc2? 5300e? 555 pc2? 5300u? 555 pc2? 5300u? 555 pc2? 5300e? 555 pc2? 5300e? 555 jedec spd revision rev. 1.2 rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 71 10202006-l0sm-feyt 43 t ck.max [ns] 80 80 80 80 80 80 44 t dqsq.max [ns] 18 18 18 18 18 18 45 t qhs.max [ns] 22 22 22 22 22 22 46 pll relock time 00 00 00 00 00 00 47 t case.max delta / ' t 4r4w delta 505050505050 48psi(t-a) dram 7a7a7a7a7a7a 49 ' t 0 (dt0) 4b4b4b4b4b4b 50 ' t 2n (dt2n, udimm) or ' t 2q (dt2q, rdimm) 343434343434 51 ' t 2p (dt2p) 36 36 36 36 36 36 52 ' t 3n (dt3n) 27 27 27 27 27 27 53 ' t 3p.fast (dt3p fast) 4c4c4c4c4c4c 54 ' t 3p.slow (dt3p slow) 2a2a2a2a2a2a 55 ' t 4r (dt4r) / ' t 4r4w sign (dt4r4w) 4c 4c 4c 4c 4c 4c 56 ' t 5b (dt5b) 20 20 20 20 20 20 57 ' t 7 (dt7) 232323232323 58psi(ca) pll 000000000000 59psi(ca) reg 000000000000 60 ' t pll (dtpll) 000000000000 61 ' t reg (dtreg) / toggle rate 00 00 00 00 00 00 62 spd revision 12 12 12 12 12 12 63 checksum of bytes 0-62 32 32 21 21 33 33 64 manufacturer?s jedec id code (1) 7f 7f 7f 7f 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 7f 7f 7f 7f product type hys72t64000eu?3s?b2 hys72t64900eu?3s?b2 hys64t128020eu?3s?b2 hys64t128920eu?3s?b2 hys72t128020eu?3s?b2 hys72t128920eu?3s?b2 organization 512mb 512mb 1 gbyte 1 gbyte 1 gbyte 1 gbyte u 72 u 72 u 64 u 64 u 72 u 72 1 rank ( u 8) 1 rank ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) label code pc2? 5300e? 555 pc2? 5300e? 555 pc2? 5300u? 555 pc2? 5300u? 555 pc2? 5300e? 555 pc2? 5300e? 555 jedec spd revision rev. 1.2 rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 72 10202006-l0sm-feyt 66 manufacturer?s jedec id code (3) 7f 7f 7f 7f 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 7f 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 00 00 00 72 module manufacturer location xx xx xx xx xx xx 73 product type, char 1 37 37 36 36 37 37 74 product type, char 2 32 32 34 34 32 32 75 product type, char 3 54 54 54 54 54 54 76 product type, char 4 36 36 31 31 31 31 77 product type, char 5 34 34 32 32 32 32 78 product type, char 6 30 39 38 38 38 38 79 product type, char 7 30 30 30 39 30 39 80 product type, char 8 30 30 32 32 32 32 81 product type, char 9 45 45 30 30 30 30 82 product type, char 10 55 55 45 45 45 45 83 product type, char 11 33 33 55 55 55 55 84 product type, char 12 53 53 33 33 33 33 85 product type, char 13 42 42 53 53 53 53 86 product type, char 14 32 32 42 42 42 42 87 product type, char 15 20 20 32 32 32 32 88 product type, char 16 20 20 20 20 20 20 product type hys72t64000eu?3s?b2 hys72t64900eu?3s?b2 hys64t128020eu?3s?b2 hys64t128920eu?3s?b2 hys72t128020eu?3s?b2 hys72t128920eu?3s?b2 organization 512mb 512mb 1 gbyte 1 gbyte 1 gbyte 1 gbyte u 72 u 72 u 64 u 64 u 72 u 72 1 rank ( u 8) 1 rank ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) label code pc2? 5300e? 555 pc2? 5300e? 555 pc2? 5300u? 555 pc2? 5300u? 555 pc2? 5300e? 555 pc2? 5300e? 555 jedec spd revision rev. 1.2 rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 73 10202006-l0sm-feyt 89 product type, char 17 20 20 20 20 20 20 90 product type, char 18 20 20 20 20 20 20 91 module revision code 2x 0x 2x 0x 2x 0x 92 test program revisi on code xx xx xx xx xx xx 93 module manufacturing date year xx xx xx xx xx xx 94 module manufacturing date week xx xx xx xx xx xx 95 - 98 module serial number xx xx xx xx xx xx 99 - 127 not used 00 00 00 00 00 00 128 - 255 blank for customer use ff ff ff ff ff ff product type hys72t64000eu?3s?b2 hys72t64900eu?3s?b2 hys64t128020eu?3s?b2 hys64t128920eu?3s?b2 hys72t128020eu?3s?b2 hys72t128920eu?3s?b2 organization 512mb 512mb 1 gbyte 1 gbyte 1 gbyte 1 gbyte u 72 u 72 u 64 u 64 u 72 u 72 1 rank ( u 8) 1 rank ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) label code pc2? 5300e? 555 pc2? 5300e? 555 pc2? 5300u? 555 pc2? 5300u? 555 pc2? 5300e? 555 pc2? 5300e? 555 jedec spd revision rev. 1.2 rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 74 10202006-l0sm-feyt table 33 hys64t[32/64]x00eu-3.7-b2 product type hys64t32000eu?3.7?b2 hys64t32900eu?3.7?b2 hys64t64000eu?3.7?b2 hys64t64900eu?3.7?b2 organization 256mb 256mb 512mb 512mb u 64 u 64 u 64 u 64 1 rank ( u 16) 1 rank ( u 16) 1 rank ( u 8) 1 rank ( u 8) label code pc2? 4200u?444 pc2? 4200u?444 pc2? 4200u?444 pc2? 4200u?444 jedec spd revision rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex 0 programmed spd bytes in eeprom 80 80 80 80 1 total number of bytes in eeprom 08 08 08 08 2 memory type (ddr2) 08 08 08 08 3 number of row addresses 0d 0d 0e 0e 4 number of column addresses 0a 0a 0a 0a 5 dimm rank and stacking information 60 60 60 60 6 data width 40 40 40 40 7 not used 00 00 00 00 8 interface voltage level 05 05 05 05 9 t ck @ cl max (byte 18) [ns] 3d 3d 3d 3d 10 t ac sdram @ cl max (byte 18) [ns] 50 50 50 50 11 error correction support (non-ecc, ecc) 00 00 00 00 12 refresh rate and type 82 82 82 82 13 primary sdram width 10 10 08 08 14 error checking sdram width 00 00 00 00 15 not used 00 00 00 00 16 burst length supported 0c 0c 0c 0c 17 number of banks on sdram device 04 04 04 04 18 supported cas latencies 38 38 38 38 19 dimm mechanical characteristics 01 01 01 01 20 dimm type information 02 02 02 02 21 dimm attributes 00 00 00 00 22 component attributes 07 07 07 07
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 75 10202006-l0sm-feyt 23 t ck @ cl max -1 (byte 18) [ns] 3d 3d 3d 3d 24 t ac sdram @ cl max -1 [ns] 50 50 50 50 25 t ck @ cl max -2 (byte 18) [ns] 50 50 50 50 26 t ac sdram @ cl max -2 [ns] 60 60 60 60 27 t rp.min [ns] 3c 3c 3c 3c 28 t rrd.min [ns] 28 28 1e 1e 29 t rcd.min [ns] 3c 3c 3c 3c 30 t ras.min [ns] 2d 2d 2d 2d 31 module density per rank 40 40 80 80 32 t as.min and t cs.min [ns] 25 25 25 25 33 t ah.min and t ch.min [ns] 37 37 37 37 34 t ds.min [ns] 10 10 10 10 35 t dh.min [ns] 22 22 22 22 36 t wr.min [ns] 3c 3c 3c 3c 37 t wtr.min [ns] 1e 1e 1e 1e 38 t rtp.min [ns] 1e 1e 1e 1e 39 analysis characteristics 00 00 00 00 40 t rc and t rfc extension 00000000 41 t rc.min [ns] 3c 3c 3c 3c 42 t rfc.min [ns] 69 69 69 69 43 t ck.max [ns] 80 80 80 80 44 t dqsq.max [ns] 1e 1e 1e 1e 45 t qhs.max [ns] 28 28 28 28 46 pll relock time 00 00 00 00 47 t case.max delta / ' t 4r4w delta 54 54 50 50 48 psi(t-a) dram 7a 7a 7a 7a product type hys64t32000eu?3.7?b2 hys64t32900eu?3.7?b2 hys64t64000eu?3.7?b2 hys64t64900eu?3.7?b2 organization 256mb 256mb 512mb 512mb u 64 u 64 u 64 u 64 1 rank ( u 16) 1 rank ( u 16) 1 rank ( u 8) 1 rank ( u 8) label code pc2? 4200u?444 pc2? 4200u?444 pc2? 4200u?444 pc2? 4200u?444 jedec spd revision rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 76 10202006-l0sm-feyt 49 ' t 0 (dt0) 5b 5b 43 43 50 ' t 2n (dt2n, udimm) or ' t 2q (dt2q, rdimm) 2c 2c 2c 2c 51 ' t 2p (dt2p) 36 36 36 36 52 ' t 3n (dt3n) 21 21 21 21 53 ' t 3p.fast (dt3p fast) 41414141 54 ' t 3p.slow (dt3p slow) 2a2a2a2a 55 ' t 4r (dt4r) / ' t 4r4w sign (dt4r4w) 4c 4c 40 40 56 ' t 5b (dt5b) 1e 1e 1e 1e 57 ' t 7 (dt7) 35352222 58 psi(ca) pll 00 00 00 00 59 psi(ca) reg 00 00 00 00 60 ' t pll (dtpll) 00000000 61 ' t reg (dtreg) / toggle rate 00 00 00 00 62 spd revision 12 12 12 12 63 checksum of bytes 0-62 40 40 34 34 64 manufacturer?s jedec id code (1) 7f 7f 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 7f 7f 66 manufacturer?s jedec id code (3) 7f 7f 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 00 72 module manufacturer location xx xx xx xx 73 product type, char 1 36 36 36 36 74 product type, char 2 34 34 34 34 product type hys64t32000eu?3.7?b2 hys64t32900eu?3.7?b2 hys64t64000eu?3.7?b2 hys64t64900eu?3.7?b2 organization 256mb 256mb 512mb 512mb u 64 u 64 u 64 u 64 1 rank ( u 16) 1 rank ( u 16) 1 rank ( u 8) 1 rank ( u 8) label code pc2? 4200u?444 pc2? 4200u?444 pc2? 4200u?444 pc2? 4200u?444 jedec spd revision rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 77 10202006-l0sm-feyt 75 product type, char 3 54 54 54 54 76 product type, char 4 33 33 36 36 77 product type, char 5 32 32 34 34 78 product type, char 6 30 39 30 39 79 product type, char 7 30 30 30 30 80 product type, char 8 30 30 30 30 81 product type, char 9 45 45 45 45 82 product type, char 10 55 55 55 55 83 product type, char 11 33 33 33 33 84 product type, char 12 2e 2e 2e 2e 85 product type, char 13 37 37 37 37 86 product type, char 14 42 42 42 42 87 product type, char 15 32 32 32 32 88 product type, char 16 20 20 20 20 89 product type, char 17 20 20 20 20 90 product type, char 18 20 20 20 20 91 module revision code 2x 0x 2x 0x 92 test program revision code xx xx xx xx 93 module manufacturing date year xx xx xx xx 94 module manufacturing date week xx xx xx xx 95 - 98 module serial number xx xx xx xx 99 - 127 not used 00 00 00 00 128 - 255 blank for customer use ff ff ff ff product type hys64t32000eu?3.7?b2 hys64t32900eu?3.7?b2 hys64t64000eu?3.7?b2 hys64t64900eu?3.7?b2 organization 256mb 256mb 512mb 512mb u 64 u 64 u 64 u 64 1 rank ( u 16) 1 rank ( u 16) 1 rank ( u 8) 1 rank ( u 8) label code pc2? 4200u?444 pc2? 4200u?444 pc2? 4200u?444 pc2? 4200u?444 jedec spd revision rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 78 10202006-l0sm-feyt table 34 hys[64/72]t[64/128]xx0eu-3.7-b2 product type hys72t64000eu?3.7?b2 hys72t64900eu?3.7?b2 hys64t128020eu?3.7?b2 hys64t128920eu?3.7?b2 hys72t128020eu?3.7?b2 hys72t128920eu?3.7?b2 organization 512mb 512mb 1 gbyte 1 gbyte 1 gbyte 1 gbyte u 72 u 72 u 64 u 64 u 72 u 72 1 rank ( u 8) 1 rank ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) label code pc2? 4200e? 444 pc2? 4200e? 444 pc2? 4200u? 444 pc2? 4200u? 444 pc2? 4200e? 444 pc2? 4200e? 444 jedec spd revision rev. 1.2 rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hex hex 0 programmed spd bytes in eeprom 80 80 80 80 80 80 1 total number of bytes in eeprom 08 08 08 08 08 08 2 memory type (ddr2) 08 08 08 08 08 08 3 number of row addresses 0e 0e 0e 0e 0e 0e 4 number of column addresses 0a 0a 0a 0a 0a 0a 5 dimm rank and stacking information 60 60 61 61 61 61 6 data width 484840404848 7 not used 00 00 00 00 00 00 8 interface voltage level 05 05 05 05 05 05 9 t ck @ cl max (byte 18) [ns] 3d 3d 3d 3d 3d 3d 10 t ac sdram @ cl max (byte 18) [ns] 50 50 50 50 50 50 11 error correction support (non-ecc, ecc) 02 02 00 00 02 02 12 refresh rate and type 82 82 82 82 82 82 13 primary sdram width 08 08 08 08 08 08 14 error checking sdram width 08 08 00 00 08 08 15 not used 00 00 00 00 00 00 16 burst length supported 0c 0c 0c 0c 0c 0c 17 number of banks on sdram device 04 04 04 04 04 04 18 supported cas latencies 38 38 38 38 38 38 19 dimm mechanical characteristics 01 01 01 01 01 01
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 79 10202006-l0sm-feyt 20dimm type information 020202020202 21 dimm attributes 00 00 00 00 00 00 22 component attributes 07 07 07 07 07 07 23 t ck @ cl max -1 (byte 18) [ns] 3d 3d 3d 3d 3d 3d 24 t ac sdram @ cl max -1 [ns] 50 50 50 50 50 50 25 t ck @ cl max -2 (byte 18) [ns] 50 50 50 50 50 50 26 t ac sdram @ cl max -2 [ns] 60 60 60 60 60 60 27 t rp.min [ns] 3c 3c 3c 3c 3c 3c 28 t rrd.min [ns] 1e 1e 1e 1e 1e 1e 29 t rcd.min [ns] 3c 3c 3c 3c 3c 3c 30 t ras.min [ns] 2d 2d 2d 2d 2d 2d 31 module density per rank 80 80 80 80 80 80 32 t as.min and t cs.min [ns] 25 25 25 25 25 25 33 t ah.min and t ch.min [ns] 37 37 37 37 37 37 34 t ds.min [ns] 10 10 10 10 10 10 35 t dh.min [ns] 22 22 22 22 22 22 36 t wr.min [ns] 3c 3c 3c 3c 3c 3c 37 t wtr.min [ns] 1e 1e 1e 1e 1e 1e 38 t rtp.min [ns] 1e 1e 1e 1e 1e 1e 39 analysis characteristics 00 00 00 00 00 00 40 t rc and t rfc extension 000000000000 41 t rc.min [ns] 3c 3c 3c 3c 3c 3c 42 t rfc.min [ns] 69 69 69 69 69 69 product type hys72t64000eu?3.7?b2 hys72t64900eu?3.7?b2 hys64t128020eu?3.7?b2 hys64t128920eu?3.7?b2 hys72t128020eu?3.7?b2 hys72t128920eu?3.7?b2 organization 512mb 512mb 1 gbyte 1 gbyte 1 gbyte 1 gbyte u 72 u 72 u 64 u 64 u 72 u 72 1 rank ( u 8) 1 rank ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) label code pc2? 4200e? 444 pc2? 4200e? 444 pc2? 4200u? 444 pc2? 4200u? 444 pc2? 4200e? 444 pc2? 4200e? 444 jedec spd revision rev. 1.2 rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 80 10202006-l0sm-feyt 43 t ck.max [ns] 80 80 80 80 80 80 44 t dqsq.max [ns] 1e 1e 1e 1e 1e 1e 45 t qhs.max [ns] 28 28 28 28 28 28 46 pll relock time 00 00 00 00 00 00 47 t case.max delta / ' t 4r4w delta 505050505050 48psi(t-a) dram 7a7a7a7a7a7a 49 ' t 0 (dt0) 434343434343 50 ' t 2n (dt2n, udimm) or ' t 2q (dt2q, rdimm) 2c2c2c2c2c2c 51 ' t 2p (dt2p) 36 36 36 36 36 36 52 ' t 3n (dt3n) 21 21 21 21 21 21 53 ' t 3p.fast (dt3p fast) 414141414141 54 ' t 3p.slow (dt3p slow) 2a2a2a2a2a2a 55 ' t 4r (dt4r) / ' t 4r4w sign (dt4r4w) 40 40 40 40 40 40 56 ' t 5b (dt5b) 1e 1e 1e 1e 1e 1e 57 ' t 7 (dt7) 222222222222 58psi(ca) pll 000000000000 59psi(ca) reg 000000000000 60 ' t pll (dtpll) 000000000000 61 ' t reg (dtreg) / toggle rate 00 00 00 00 00 00 62 spd revision 12 12 12 12 12 12 63 checksum of bytes 0-62 46 46 35 35 47 47 64 manufacturer?s jedec id code (1) 7f 7f 7f 7f 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 7f 7f 7f 7f product type hys72t64000eu?3.7?b2 hys72t64900eu?3.7?b2 hys64t128020eu?3.7?b2 hys64t128920eu?3.7?b2 hys72t128020eu?3.7?b2 hys72t128920eu?3.7?b2 organization 512mb 512mb 1 gbyte 1 gbyte 1 gbyte 1 gbyte u 72 u 72 u 64 u 64 u 72 u 72 1 rank ( u 8) 1 rank ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) label code pc2? 4200e? 444 pc2? 4200e? 444 pc2? 4200u? 444 pc2? 4200u? 444 pc2? 4200e? 444 pc2? 4200e? 444 jedec spd revision rev. 1.2 rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 81 10202006-l0sm-feyt 66 manufacturer?s jedec id code (3) 7f 7f 7f 7f 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 7f 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 00 00 00 72 module manufacturer location xx xx xx xx xx xx 73 product type, char 1 37 37 36 36 37 37 74 product type, char 2 32 32 34 34 32 32 75 product type, char 3 54 54 54 54 54 54 76 product type, char 4 36 36 31 31 31 31 77 product type, char 5 34 34 32 32 32 32 78 product type, char 6 30 39 38 38 38 38 79 product type, char 7 30 30 30 39 30 39 80 product type, char 8 30 30 32 32 32 32 81 product type, char 9 45 45 30 30 30 30 82 product type, char 10 55 55 45 45 45 45 83 product type, char 11 33 33 55 55 55 55 84 product type, char 12 2e 2e 33 33 33 33 85 product type, char 13 37 37 2e 2e 2e 2e 86 product type, char 14 42 42 37 37 37 37 87 product type, char 15 32 32 42 42 42 42 88 product type, char 16 20 20 32 32 32 32 product type hys72t64000eu?3.7?b2 hys72t64900eu?3.7?b2 hys64t128020eu?3.7?b2 hys64t128920eu?3.7?b2 hys72t128020eu?3.7?b2 hys72t128920eu?3.7?b2 organization 512mb 512mb 1 gbyte 1 gbyte 1 gbyte 1 gbyte u 72 u 72 u 64 u 64 u 72 u 72 1 rank ( u 8) 1 rank ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) label code pc2? 4200e? 444 pc2? 4200e? 444 pc2? 4200u? 444 pc2? 4200u? 444 pc2? 4200e? 444 pc2? 4200e? 444 jedec spd revision rev. 1.2 rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 82 10202006-l0sm-feyt 89 product type, char 17 20 20 20 20 20 20 90 product type, char 18 20 20 20 20 20 20 91 module revision code 2x 0x 2x 0x 2x 0x 92 test program revisi on code xx xx xx xx xx xx 93 module manufacturing date year xx xx xx xx xx xx 94 module manufacturing date week xx xx xx xx xx xx 95 - 98 module serial number xx xx xx xx xx xx 99 - 127 not used 00 00 00 00 00 00 128 - 255 blank for customer use ff ff ff ff ff ff product type hys72t64000eu?3.7?b2 hys72t64900eu?3.7?b2 hys64t128020eu?3.7?b2 hys64t128920eu?3.7?b2 hys72t128020eu?3.7?b2 hys72t128920eu?3.7?b2 organization 512mb 512mb 1 gbyte 1 gbyte 1 gbyte 1 gbyte u 72 u 72 u 64 u 64 u 72 u 72 1 rank ( u 8) 1 rank ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) 2 ranks ( u 8) label code pc2? 4200e? 444 pc2? 4200e? 444 pc2? 4200u? 444 pc2? 4200u? 444 pc2? 4200e? 444 pc2? 4200e? 444 jedec spd revision rev. 1.2 rev. 1. 2 rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hex hex
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 83 10202006-l0sm-feyt 5 package outlines figure 6 package outline l-dim-240-3 raw card c notes 1. drawing according to iso 8015 2. dimensions in mm 3. general tolerances +/- 0.15 * /' % & $ & ? 0 $; % ? % x u u p d [ d o o r z h g ? $ % & ' h w d l o r i f r q w d f w v ? $ ? [
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 84 10202006-l0sm-feyt figure 7 package outline l-dim-240-6 raw card f notes 1. drawing according to iso 8015 2. dimensions in mm 3. general tolerances +/- 0.15 * /' & % $ ? % ? ? ? ? ? 0 $; & ? ? ? $ ? ? ? 0 , 1 % x u u p d [ d o o r z h g ' h w d l o r i f r q w d f w v & ? $ % ?
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 85 10202006-l0sm-feyt figure 8 package outline l-dim-240-7 raw card g notes 1. drawing according to iso 8015 2. dimensions in mm 3. general tolerances +/- 0.15 * /' & % $ ? % ? ? ? ? ? 0 $; & ? ? ? $ ? ? ? 0 , 1 % x u u p d [ d o o r z h g ' h w d l o r i f r q w d f w v & ? $ % ?
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 86 10202006-l0sm-feyt figure 9 package outline l-dim-240-8 raw card d notes 1. drawing according to iso 8015 2. dimensions in mm 3. general tolerances +/- 0.15 * /' & % $ ? % ? ? ? ? ? 0 $; & ? ? ? $ ? ? ? 0 , 1 % x u u p d [ d o o r z h g ' h w d l o r i f r q w d f w v & ? $ % ?
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 87 10202006-l0sm-feyt figure 10 package outline l-dim-240-9 raw card e notes 1. drawing according to iso 8015 2. dimensions in mm 3. general tolerances +/- 0.15 * /' & % $ ? % ? ? ? ? ? 0 $; & ? ? ? $ ? ? ? 0 , 1 % x u u p d [ d o o r z h g ' h w d l o r i f r q w d f w v & ? $ % ?
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 88 10202006-l0sm-feyt 6 product type nomenclature qimonda?s nomenclature uses simple coding combined with some proprietary coding. table 35 provides examples for module and component product type number as well as the field number. the detailed field description together with possible values and coding explanation is listed for modules in table 36 and for components in table 37 . table 35 nomenclature fields and examples table 36 ddr2 dimm nomenclature example for field number 1234567891011 micro-dimm hys 64 t 64/128 0 2 0 k m ?5 ?a ddr2 dram hyb 18 t 512/1g 16 0 a c ?5 field description values coding 1 qimonda module prefix hys constant 2 module data width [bit] 64 non-ecc 72 ecc 3 dram technology t ddr2 4 memory density per i/o [mbit]; module density 1) 32 256 mbyte 64 512 mbyte 128 1 gbyte 256 2 gbyte 512 4 gbyte 5 raw card generation 0 .. 9 look up table 6 number of module ranks 0, 2, 4 1, 2, 4 7 product variations 0 .. 9 look up table 8 package, lead-free status a .. z look up table 9 module type d so- d imm m m icro-dimm r r egistered u u nbuffered f f ully buffered
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 89 10202006-l0sm-feyt table 37 ddr2 dram nomenclature 10 speed grade ?19f pc2?8500 6?6?6 ?1.9 pc2?8500 7?7?7 ?25f pc2?6400 5?5?5 ?2.5 pc2?6400 6?6?6 ?3 pc2?5300 4?4?4 ?3s pc2?5300 5?5?5 ?3.7 pc2?4200 4?4?4 ?5 pc2?3200 3?3?3 11 die revision ?a first ?b second 1) multiplying ?memory density per i/o? with ?module data width? and dividing by 8 for non-ecc and 9 for ecc modules gives the o verall module memory density in mbytes as listed in column ?coding?. field description values coding 1 qimonda component prefix hyb constant 2 interface voltage [v] 18 sstl_18 3 dram technology t ddr2 4 component density [mbit] 256 256 mbit 512 512 mbit 1g 1 gbit 2g 2 gbit 5+6 number of i/os 40 u 4 80 u 8 16 u 16 7 product variations 0 .. 9 look up table 8 die revision a first b second 9 package, lead-free stat us c fbga, lead-containing f fbga, lead-free 10 speed grade ?19f pc2?8500 6?6?6 ?1.9 pc2?8500 7?7?7 ?25f pc2?6400 5?5?5 ?2.5 pc2?6400 6?6?6 ?3 pc2?5300 4?4?4 ?3s pc2?5300 5?5?5 ?3.7 pc2?4200 4?4?4 ?5 pc2?3200 3?3?3 field description values coding
hys[64/72]t[32/64/ 128]xxxeu-[25f/2.5/3/3s/3.7]-b2 unbuffered ddr2 sdram module internet data sheet rev. 1.01, 2008-01 90 10202006-l0sm-feyt contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin configurations and block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 speed grade definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 component ac timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5 odt ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.6 i dd specifications and conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4 spd codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6 product type nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
edition 2008-01 published by qimonda ag gustav-heinemann-ring 212 d-81739 mnchen, germany ? qimonda ag 2008. all rights reserved. legal disclaimer the information given in this internet data sheet shall in no ev ent be regarded as a gua rantee of conditions or characteristics (?beschaffenheitsgarantie?). with respect to any examples or hi nts given herein, any typical values stated herein and/or any information regarding the application of the device, qimonda hereby disclaims any and all warranties and liabilities of any kin d, including without limitation warranties of non-infringem ent of intellectual property rights of any third party. information for further information on technology, delivery terms and conditio ns and prices please contact your nearest qimonda office. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest qimonda office. qimonda components may only be used in life-support devices or systems with the express writte n approval of qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support devi ce or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is re asonable to assume that the he alth of the user or other persons may be endangered. www.qimonda.com internet data sheet

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